USA As Represented by Secretary of the Navy

Northrop Grumman Systems Corporation

John Bradley Boos

Brian R Bennett

Nicolas A Papanicolaou

James G Champlain

Mario Ancona

Richard Magno

Theresa F Chick

Jeffrey Ming-Jer Yang

Doewon Park

Jay D Crawford

Yeong-Chang Chou

Walter Kruppa

Jane Lee

Tung H Weng

Jonathan L Shaw

Bradford B Pate

Harry B Dietrich

Paul M Campbell

Gordon W Anderson

Ming-Jey Yang

Ingham A Mack

Harvey S Newman

Kevin Jensen

Nicholas A Papanicolou

Byoung-don Kong

Brad P Tinkham

Joan E Yater

David I Ma

A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.

Vacuum transistor structure using graphene edge field emitter and screen electrode

An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.

Strained InGaAs quantum wells for complementary transistors

A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of InAlAs on an InP substrate, where the InAlAs is lattice matched to InP, followed by an AlAsSbbuffer layer on the InAlAs layer, an AlAsSbspacer layer on the AlAsSbbuffer layer, a GaSb quantum well layer on the AlAsSbspacer layer, an AlAsSbbarrier layer on the GaSb quantum well layer, an InAlSb etch-stop layer on the AlAsSbbarrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.

Low-resistivity p-type GaSb quantum wells

An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.

Antimonide-based compound semiconductor with titanium tungsten stack

A complementary metal oxide semiconductor (CMOS) device in which a single InGaSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InGaSb layer is part of a heterostructure that includes a Te-delta doped AlGaSb layer above the InGaSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlGaSb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlGaSb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InGaSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

n- and p-channel field effect transistors with single quantum well for complementary circuits

N- and p-channel field-effect transistors with single quantum well for complementary circuits

This disclosure describes a semiconductor device that can be used as a mixer at RF frequencies extending from a few tens of GHz into the THz frequency range. The device is composed of narrow bandgap semiconductors grown by solid source molecular beam epitaxy. The device can comprise a GaSb substrate, a AlSb layer on the GaSb substrate, a InAlAsSblayer, on the AlSb layer and wherein the InAlAsSbcomprises varying levels of Te doping, a InGaSb layer on the InAlAsSblayer, wherein the InGaSb layer is Be doped, wherein the first section of the InAlAsSblayer has is Te doped, wherein the second section of the InAlAsSblayer has a grade in Te concentration, and wherein the third section of the InAlAsSblayer is Te doped.

P-N junction for use as an RF mixer from GHZ to THZ frequencies

This invention pertains to heterojunction bipolar transistors containing a semiconductor substrate, a buffer layer of an antimony-based material deposited on the substrate, a sub-collector layer of an antimony-based material deposited on the buffer layer, a collector layer of an antimony-based material deposited on the sub-collector layer, a base layer of an antimony-based material deposited on the collector layer, an emitter layer of an antimony-based material deposited on the base layer, and a cap layer of an antimony-based material deposited on the emitter layer.

InAlAsSb/InGaSb and InAlPSb/InGaSb heterojunction bipolar transistors

This invention pertains to an electronic device containing a semi-insulating substrate, a buffer layer of an antimony-based material disposed on said substrate, a channel layer of InAsSbmaterial disposed on said buffer layer, a barrier layer of an antimony-based disposed on said channel layer, and a cap layer of InAsSbmaterial disposed on said barrier layer, wherein the device can have frequency of on the order of 500 GHz and a reduced power dissipation.

High electron mobility transistors with Sb-based channels

An electronic semiconductor device comprising a semiconductor base deposited on a semiconductor substrate by means of molecular beam epitaxy and source, drain and gate disposed on the base in a spaced relationghip to each other, the source and the drain comprising Pd/barrier/Au layers with the palladium layer being in contact with the device. The device is fabricated conventionally except the heat treating is at above about 170&deg; C. for &frac14;-10 hours sufficient for the palladium layer to react with the base yielding reduced contact and access resistances and a narrower spacing between source and drain.

Metalization of electronic semiconductor devices

This invention pertains to more sensitive and more stable electronic devices which can sense electrical and magnetic fields. The devices are characterized by InAs channels confined on both sides thereof by a wide band gap AlSb material; protective layers above the AlSb material; modulation doping above the AlSb material; and layers of the InAs channel material containing 1 to 99 mol percent antimony, with the channel material being deposited in the form of alternating monolayers of InSb and InAs, of a ternary mixture of InAsSb.

Modified InAs hall elements

An electronic device characterized by a GaAs substrate and a base disposed n the substrate, the base comprising InAs channel layer, AlSb layer above the channel layer, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer containing at least In, Al, and As disposed above the AlSb channel layer, InAs cap layer disposed above and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer disposed below the InAs channel layer and in contact with the substrate, p.sup.+ GaSb layer disposed within the AlSb layer, Schottky gate with a pad disposed on and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer, at least one ohmic contact disposed on the InAs cap layer, and a trench extending through the base to the substrate isolating the gate bonding pad from the device and providing a gate air bridge which prevents contact between the gate and the InAs layer. The gate air bridge fabrication is accomplished by a liquid etchant containing more than half, on volume basis, of concentrated lactic acid or acetic acid with remainder hydrogen peroxide and concentrated hydrofluoric acid. The etchant attacks InAs, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y, AlSb, and GaSb but does not attack GaAs and Au-based alloys.

Electronic devices with InAlAsSb/AlSb barrier

A new planar, fully ion-implanted indium phosphide junction FET (JFET) fabrication process, utilizing n.sup.+ source-drain implantation, Be and Be/P p.sup.+ gate implantation, and nitride-registered gate metallization.

Growing community of inventors

Springfield, VA, United States of America

John Bradley Boos