Duet Microelectronics, Inc.

John Bayruns

Robert J Bayruns

Ashok T Ramu

Keun-Yong Ban

The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.

Dual-operation depletion/enhancement mode high electron mobility transistor

Fabrication of a dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistor (HEMT) called a threshold control terminal HEMT (TCT-HEMT) is performed which reduces capacitance between the TCT electrode and the source and drain electrodes of a TCT-HEMT, since such a capacitance may be parasitic, and which fabricates a TCT-HEMT capable of high-frequency operation. A method for fabricating a field-effect transistor (FET) includes: providing a substrate; disposing a back barrier on the substrate to form a base stack; forming a doped layer on the base stack; grow additional layers, including a threshold-control terminal (TCT) access layer; etch a pattern in at least one of the doped layer and the additional layers; and disposing a TCT contact on the TCT access layer.

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Raritan, NJ, United States of America

John Bayruns