Cufer Asset Ltd. L.l.c.

Other

Xanoptix Inc.

Teraconnect, Incorporated

Cubic Wafer, Inc.

Altera Corporation

Sensors Unlimited

Leland Stanford Junior University

Xanoptrix, Inc.

Teraconnect, Incoporated

Cufer Assett Ltd. L.l.c.

John A Trezza

Keith Kang

Gregory Dudoff

Greg Dudoff

Roger Dugas

John J Callahan

Mark Czoschke

Richard Stack

Ronald E Olson

Ross Frushour

Abhay Misra

Martin Harris Ettenberg

Gregory K Duddoff

James S Harris, Jr

Mani Sundaram

Richard J Williams

Glenn Richard Thoren

Harald Hamster

Theodore J Wyman

Timothy P Boggess

Theodore J (Ted) Wyman

Martin Morf

Mohamed Diagne

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

Tooling for coupling multiple electronic chips

An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.

Contact-based encapsulation

A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells.

Low noise hybridized detector using charge transfer

A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.

Inverse chip connector

In one aspect, the present invention provides photodetectors and components thereof having multi-spectral sensing capabilities. In some embodiments, photodetectors of the present invention provide a first photosensitive element comprising at least one accessway extending through the element and an electrical connection at least partially disposed in the accessway, the electrical connection accessible for receiving a second photosensitive element.

Multicolor detectors and applications thereof

An apparatus involves a semiconductor wafer that has been back-end processed, the semiconductor wafer including a substrate, electronic devices and multiple metalization layers, a via extending from an outer surface of the substrate through the substrate to a metalization layer from among the multiple metalization layers, and an electrically conductive material within the via, the electrically conductive material forming an electrically conductive path from the metalization layer to the outer surface. A method of processing a semiconductor wafer that has been front-end and back-end processed involves forming a via in the semiconductor wafer extending from a surface of the wafer, into and through semiconductor material, to a metalization layer formed during the back-end processing by etching the semiconductor wafer; and making the via electrically conductive so as to form an electrical path within the via extending from the surface of the wafer to the metalization layer.

Processed wafer via

A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electrically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25 &#x3bc;m. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less than 25 &#x3bc;m.

Method of making a capacitive sensor

A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.

Triaxial through-chip connection

A chip has a wafer portion of a first coefficient of thermal expansion, the wafer portion including at least one via defined by a peripheral sidewall, an insulating region having second average coefficient of thermal expansion, located within the via and covering at least a portion of the peripheral sidewall to a first thickness, a metallic region having a third average coefficient of thermal expansion, located within the via and covering the insulator to a second thickness, the first thickness and second thickness being selected such that expansion of the combination of the insulator and the metal due to heat will match the expansion of the wafer portion as a result of the combined effect of the first and second thicknesses and their respective second and third average coefficients of thermal expansion.

Thermally balanced via

A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Process for chip capacitive coupling

An apparatus for use with multiple chips having multiple posts as to engage at least a portion of a surface of one of the multiple chips, a frame configured to releasably constrain each of the posts so that, when unconstrained, each individual post can contact an individual chip and, when constrained, will allow a uniform vertical force to be applied to the chips.

Pin-type chip tooling

An apparatus for use with multiple individual chips having a rigid plate, and a deformable membrane located on the plate, the deformable membrane having a thickness sufficient to allow the deformable membrane to peripherally conform to each of the individual multiple chips irrespective of any difference in height among the multiple individual chips and to prevent each of the multiple individual chips from moving in a lateral direction, the deformable membrane being configured to uniformly transfer a vertical force, applied to the rigid plate, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded during a connect and release cycle without causing damage to the individual chips or bonding surface.

Growing community of inventors

Nashua, NH, United States of America

John A Trezza