Globalfoundries Inc.

Johannes F Groschopf

Andy C Wei

Andreas Ott

Vivien Schroeder

Klaus Hempel

Berthold Reimer

Patrick Press

Katja Steffen

Ralf Richter

Thilo Scheiper

Thomas Werner

Jens Heinrich

Martin Trentzsch

Andrew Michael Waite

Gunter Grasshoff

Frank Seliger

Axel Kiesel

Rico Hueselitz

Christopher M Prindle

Marco Kitsche

Manfred Heinz

In a replacement gate approach, the dielectric material for laterally encapsulating the gate electrode structures may be provided in the form of a first interlayer dielectric material having superior gap filling capabilities and a second interlayer dielectric material that provides high etch resistivity and robustness during a planarization process. In this manner, undue material erosion upon replacing the placeholder material may be avoided, which results in reduced yield loss and superior device uniformity.

Replacement gate approach for high-k metal gate stacks by using a multi-layer contact level

Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

Self-aligned multiple gate transistor formed on a bulk substrate

For complex CMP processes requiring the removal of different dielectric materials, possibly in the presence of a polysilicon material, a slurry material may be adapted at the point of use by selecting an appropriate pH value and avoiding agglomeration of the abrasive particles. The in situ preparation of the slurry material may also enable a highly dynamic adaptation of the removal conditions, for instance when exposing the polysilicon material of gate electrode structures in replacement gate approaches.

Planarization of a material system in a semiconductor device by using a non-selective in situ prepared slurry

A polishing pad for an electrochemical planarization tool comprises a patterned surface that forms appropriate electrolyte flow channels for directing an electrolyte from the center to the periphery thereof. Consequently, a continuous electrolyte flow may be established, thereby significantly reducing the accumulation of contaminants in the polishing pad, thereby contributing to enhanced process uniformity so that frequent rinsing of the polishing pad and replacement of the electrolyte solution may be avoided.

Electrochemical planarization system comprising enhanced electrolyte flow

In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.

Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors

In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.

Method of forming CMOS device having gate insulation layers of different type and thickness

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Radebeul, Germany

Johannes F Groschopf