Intel Corporation

Other

Mobileye Vision Technologies Ltd.

Tahoe Research, Ltd.

Santa Clara

Johanna M Swan

Adel A Elsherbini

Shawna M Liff

Feras Eid

Aleksandar Aleksov

Georgios C Dogiamis

Telesphor Kamgaing

Sasha N Oster

Henning Braunisch

Veronica Aleman Strong

Valluri Ramana Rao

Thomas L Sounart

Qing Ma

Gerald S Pasdast

Brandon M Rawlings

Arun Chandrasekhar

Robert L Sankman

Vijay K Nair

Kimin Jun

Krishna Bharath

Richard J Dischler

Sujit Sharan

Patrick R Morrow

Chia-Pin Chiu

John Stephen Guzek

Stefanie M Lotz

Mauro J Kobrinsky

Weng Hong Teh

Brennen Karl Mueller

Ian A Young

Van H Le

Han Wui Then

Paul B Fischer

Kevin Lai Lin

Fay Hua

Amit S Baxi

Kristof Darmawikarta

Zhiguo Qian

Islam A Salama

William J Lambert

Kishore K Chakravorty

Jimin Yao

Marko Radosavljevic

Kemal Aygun

Omkar G Karhade

Chuan Hu

Kaladhar Radhakrishnan

Quan Anh Tran

Javier Soto Gonzalez

Robert Starkston

Sergio Antonio Chan Arguedas

Thomas P Thomas

Julien Sebot

Brandon Barnett

Ravi Pillarisetty

Shahrnaz Azizi

Mark T Bohr

Dmitri E Nikonov

James S Clarke

Uygar E Avci

Ofir Degani

Jeanette M Roberts

Nitin A Deshpande

Nicole K Thomas

Sri Ranga Sai Boyapati

Eyal Fayneh

Peter Chang

Bruce A Block

Roman Caudillo

Ravi Kiran Nalla

Rajashree Raji Baskaran

Chien Chiang

Ashish Gupta

Chandra Mohan Jha

Ravi V Mahajan

Kenneth D Shoemaker

Rajendra C Dias

Robert S Chau

Gilbert W Dewey

Rita H Wouhaybi

Debendra Mallik

Tanay Karnik

Min Huang

Daoqiang Lu

Linda L Hurd

Hassnaa Moustafa

Hubert C George

Randy B Osborne

Lakshman Krishnamurthy

Pooya Tadayon

Wilfred Gomes

Zachary R Yoscovits

James Chris Matayabas, Jr

Yonggang Li

Joshua Heppner

Vivek Raghunathan

Steven N Towle

Annie Foong

Neelam Chandwani

Hyung-Jin Lee

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

Contiguous shield structures in microelectronic assemblies having hybrid bonding

An integrated circuit (IC) device structure, comprising a host chip having a device layer and one or more first metallization levels over adjacent first and second regions of the device layer. The first metallization levels are interconnected to the device layer. An interconnect chiplet is over the first metallization levels within the first region. The interconnect chiplet comprises a plurality of second metallization levels, and a plurality of third metallization levels over the first metallization levels within the second region and adjacent to the interconnect chiplet. At least one of an interconnect feature dimension or composition differs between one of the second metallization levels and an adjacent one of the third metallization levels.

Selective interconnects in back-end-of-line metallization stacks of integrated circuitry

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.

Microelectronic assemblies having backside die-to-package interconnects

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.

Direct bonding in microelectronic assemblies

Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

Composite interposer structure and method of providing same

Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.

Magnetic planar spiral and high aspect ratio inductors for power delivery in the glass-core of a package substrate

Embodiments described herein may be related to apparatuses, processes, and techniques related to via structures and/or planar structures within a glass core of a substrate to facilitate high-speed signaling with a die coupled with the substrate. In embodiments, the substrate may be coupled with an interposer to enable high-speed signaling between a compute die (or tile) and a storage die (or tile) that may be remote to the substrate. Other embodiments may be described and/or claimed.

Die coupling using a substrate with a glass core

Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.

Thermal performance in hybrid bonded 3D die stacks

Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.

Waveguide interconnect bridges

An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

Skip level vias in metallization layers for integrated circuit devices

Growing community of inventors

Scottsdale, AZ, United States of America

Johanna M Swan