Infineon Technologies Ag

Siemens Aktiengesellschaft

Johann Helneder

Markus Schwerd

Thomas Goebel

Andrea Mitchell

Martin Seck

Heinrich Körner

Martina Hommel

Wolfgang Klein

Holger Torwesten

Stefan Drexl

Heinrich Koerner

Armin Fischer

Alexander Von Glasow

Wolfgang Walter

Peter Kuecher

Heinrich Kôrner

E-Wolfgang Frank

Thomas Göbel

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

Process for producing a multifunctional dielectric layer on a substrate

An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

Integrated circuit with capacitor and method for the production thereof

An embodiment according to the present invention comprises a method for providing a self-aligned conductive structure comprising providing a first structure on a surface, wherein the first structure comprises a first and a second layer, and providing an intermediate structure on the surface, wherein the intermediate structure at least partially abuts the first structure laterally at a first lateral edge of the first structure. The method further comprises removing at least a part of the second layer, the part being adjacent to the first lateral edge, and providing the conductive structure such that the conductive structure replaces at least the removed part of the second layer and abuts the first lateral edge.

Method for providing a self-aligned conductive structure

A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

Integrated connection arrangements

Method for filling a trench in a semiconductor product is disclosed. A first material is deposited onto a semiconductor product having a surface in which at least one trench is formed. A first layer is formed within the trench and on the surface of the semiconductor product outside the trench. A second material is deposited to form a second layer above the first layer outside the trench and the trench is filled. Chemical mechanical polishing is performed so that the second layer is removed above the first layer outside the trench and whereby the first layer is at least uncovered outside the trench. Residual first material of the first layer is removed by wet-chemical etching.

Method for filling a trench in a semiconductor product

An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.

Integrated circuit having a thermally shielded electric resistor trace

A method and apparatus for measuring sheet resistivity of a layer manufactured under the influence of a plasma, wherein a current is generated using two voltage or current sources in a circuit that is composed of a first current branch, a sheet resistivity, and a second current branch. The current includes the parasitic current I.sub.P injected into the layer by the plasma, this having a first and second part which are symmetrically supplied into the two current branches which respectively have an identical resistance overall. The currents I.sub.A and I.sub.B thus actually flowing in the first and second current branch are respectively directly measured, or measured on the basis of the voltage drop-off at known precision resistors. A measured current I.sub.M which is independent of the plasma influence is calculated therefrom by averaging, and the sheet resistivity is calculated from I.sub.M and by measuring the voltage drop-off at the sheet resistivity.

Growing community of inventors

Landsham, Germany

Johann Helneder