Sandisk Technologies Inc.

Sandisk 3d LLC

Johann Alsmeier

Yanli Zhang

James K Kai

Raghuveer S Makala

Jayavel Pachamuthu

Yao-Sheng Lee

Henry Chien

Murshed Chowdhury

Masaaki Higashitani

Peter Rabkin

George Matamis

George Samachisa

Yingda Dong

Tong Zhang

Senaka Kanakamedala

Hiroyuki Ogawa

Rahul Sharangpani

Xiying Costa

Jian Feng Chen

Vinod Robert Purayath

Yan Li

Fumiaki Toyama

Man Lung Mui

Ching-Huang Lu

Zhixin Cui

Andrew C Lin

Shinsuke Yada

Kwang-Ho Kim

Peng Zhang

Christopher John Petti

Jiahui Yuan

Fei Zhou

Henry Chin

Hiroyuki Kinoshita

Seungpil Lee

Wei Zhao

Masanori Tsutsumi

Seiji Shimabukuro

Deepanshu Dutta

Xiang Yang

Dana Lee

Gerrit Jan Hemink

Steven Theodore Sprouse

Andrei Mihnea

Takashi Whitney Orimoto

Jixin Yu

Jin Liu

Zhenyu Lu

Daxin Mao

Koichi Matsuno

Sateesh Koka

Chun Ge

Wenguang Shi

Matthias Baenninger

Yuan Zhang

Kensuke Yamaguchi

Alex Mak

Akira Matsudaira

Koji Miyata

Satoshi Shimizu

Yuki Mizutani

Genta Mizuno

Sayako Nagamine

Masanori Terahara

Xiaolong Hu

Yoko Furihata

Chi-Ming Wang

Naoki Takeguchi

Zhengyi Zhang

Srikanth Ranganathan

Somesh Peri

Donovan Lee

Hiro Kinoshita

Alexander Chu

Jiyin Xu

Yung-Tin Chen

Masatoshi Nishikawa

Toru Miwa

Tatsuya Hinoue

Akio Nishida

Chun-Ming Wang

Mitsuteru Mushiga

Hisakazu Otoi

Kota Funayama

Teruo Okina

Atsushi Suyama

Ryoichi Honma

Keisuke Izumi

Yusuke Yoshida

Mitsuhiro Togo

Junichi Ariyoshi

Ryousuke Itou

Shigehiro Fujino

Yasuo Kasagi

Yujin Terasawa

Akihisa Sai

Ming Tian

Sung Tae Lee

Chenche Huang

Akira Takahashi

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

Three-dimensional nor array and method of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory opening fill structures including a respective vertical semiconductor channel and a respective memory film, and support pillar structures including a respective dummy vertical semiconductor channel, a respective dummy memory film, and a vertical stack of dielectric spacer fins located at levels of the electrically conductive layers and interposed between the electrically conductive layers and the respective dummy memory film.

Three-dimensional memory device with finned support pillar structures and method of forming the same

A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

Field effect transistors with gate fins and method of making the same

A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

Bonded semiconductor die assembly containing through-stack via structures and methods for making the same

A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region.

Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same

Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

Three-dimensional memory device with multiple types of support pillar structures and method of forming the same

Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Preventing erase disturb in NAND

A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.

Memory device using a multilayer ferroelectric stack and method of forming the same

At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

Bonded memory devices and methods of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.

Three-dimensional memory device with wiggled drain-select-level isolation structure and methods of manufacturing the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

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San Jose, CA, United States of America

Johann Alsmeier