Semiconductor Components Industries, LLC

Ami Semiconductor Belgium Bvba

Johan Camiel Julia Janssens

Moshe Agam

Jaroslav Pjencak

Agajan Suwhanov

Tomas Geurts

Sergey Velichko

Manuel H Innocent

Jaume Roig-Guitart

Jean-Paul Eggermont

Bruce Greenwood

Sallie Hose

Weize Chen

Mark Griswold

Dieter Jozef Joos

Thierry Yao

Peter Moens

Pavel Horsky

Jacques Jean Bertin

Marnix Tack

Petr Kamenicky

Herman Joris Casier

Jaroslav Pjencák

Frederick Johan G Declercq

Sam Jan Ben Willem Vermeir

David Pierre Jean Robert Levacq

Joannes Mathilde Josephus Sevenhans

Damien Luc Francois Macq

Teddy Bonnin

A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.

High voltage diode on SOI substrate with trench-modified current path

Systems and methods of the disclosed embodiments include a semiconductor device having a semiconductor substrate. The semiconductor substrate has a first major surface, an opposing second major surface, a first doped region of a first conductivity type disposed beneath the first major surface, and a semiconductor region of the first conductivity type disposed between the first doped region and the second major surface. The semiconductor device may also include a trench isolation structure, comprising a conductive trench filling enclosed by an insulating trench liner. The trench isolation structure extends from the first major surface through the first doped region and into the semiconductor region. The semiconductor device may also include a semiconductor device structure disposed with a drain structure, and a connection structure formed between the conductive trench filling of the trench isolation structure and the drain region.

Semiconductor device having optimized drain termination and method therefor

An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.

Electronic device including a semiconductor body or an isolation structure within a trench

Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.

Image sensors with vertically stacked photodiodes and vertical transfer gates

In one embodiment, a driver circuit is configured to form a Vgs of a transistor as a negative value during a time interval that a second transistor, connected to the first transistor, is being enabled.

Method of forming a semiconductor device and circuit therefor

A readout circuit for use with a Wheatstone bridge sensor. At least some of the example embodiments are methods including: driving an excitation signal in parallel through a first set of sensor elements of a Wheatstone bridge sensor and refraining from driving the excitation signal through a second set of sensor elements of the Wheatstone bridge sensor; measuring response of the first set of sensor elements, the measuring response of the first set of sensor elements creates a first measurement; and then driving the excitation signal in parallel through the second set of sensor elements of the Wheatstone bridge and refraining from driving the excitation signal through the first set of sensor elements; and measuring response of the second set of sensor elements, the measuring response of the second set of sensor elements creates a second measurement.

Methods and related systems of a readout circuit for use with a wheatstone bridge sensor

A leakage compensation circuit includes a buffer amplifier, a link coupling element, and a leakage compensation element. The buffer amplifier has an input coupled to a sense node, and an output. The link coupling element has an input coupled to the output of the buffer amplifier, and an output, wherein the link coupling element is unidirectional in a direction from the input to the output thereof. The leakage compensation element has a first current terminal coupled to the sense node, a control terminal coupled to the output of the link coupling element, and a second current terminal coupled to a reference voltage terminal.

Bidirectional leakage compensation circuits for use in integrated circuits and method therefor

In one embodiment, a method of forming a semiconductor device may include forming a sensing circuit to apply a voltage to a doped region wherein the voltage expands depletion region toward a second depletion region but substantially does not intersect the second depletion region. An embodiment may include configuring the sensing circuit to detect electrons within the doped region and to responsively assert a detection signal representing detection of the electrons wherein the sensing circuit detects the electrons while applying the voltage to the second doped region.

Method of forming a semiconductor device and current sensing circuit therefor

A circuit can comprise a transistor, a sensor, and a switch. The transistor can include a drain electrode, a gate electrode, a source electrode, and a back electrode. The sensor can be configured to detect an error condition in the transistor. The switch can be configured to change a voltage at the back electrode in response to the sensor detecting the error condition in the transistor, the change of the voltage at the back electrode reducing current flow between the drain electrode and the source electrode.

Circuit that changes voltage of back electrode of transistor based on error condition

A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.

Semiconductor device having biasing structure for self-isolating buried layer and method therefor

Rectifier circuit. At least some of the example embodiments are circuits including: an anode terminal; a cathode terminal; a field effect transistor (FET) defining a drain, source, and gate, the source coupled to the anode terminal, and the drain coupled to the cathode terminal; a diode having anode and cathode, the anode coupled to the cathode terminal; a bootstrap capacitor coupled between the cathode of the diode and the anode terminal; a FET controller coupled to the gate of the FET and a node between the diode and bootstrap capacitor; the FET controller configured to make the FET conductive as the circuit becomes forward biased, and the FET controller configured to make the FET non-conductive during periods of time when the circuit is reverse biased.

Methods and systems of a rectifier circuit

In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.

Circuit and an electronic device including a transistor and a component and a process of forming the same

A method includes configuring a transmitter to provide at least three output levels used to form an output signal. The method further includes adjusting a duration of at least one of the output levels to control an average value of the output signal independently of an amplitude of a first harmonic of the output signal.

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Asse, Belgium

Johan Camiel Julia Janssens