Globalfoundries Inc.

Infineon Technologies Ag

Joerg Radecker

Frank Jakubowski

Stephan Kronholz

Thorsten E Kammler

Hans-Juergen Thees

Christof Streck

Joanna Wasyluk

Ralf Willecke

Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.

Method of protecting STI structures from erosion during processing operations

A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.

Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process

In one example, the method includes forming a patterned etch mask above a semiconducting substrate, performing an etching process through the patterned etch mask to thereby form a trench in the substrate, performing a first deposition process to form a first layer of insulating material above the patterned etch mask and in the trench, and performing an etching process on the first layer of insulating material such that the post-etch thickness of the first layer of insulating material is less than an as-deposited thickness of the first layer of insulating material. The method also includes performing a second deposition process to form a second layer of insulating material on the etched first layer of insulating material, wherein the second layer of insulating material overfills the trench, and removing portions of the etched first layer of insulating material and the second layer of insulating material positioned above the patterned etch mask.

Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence

Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.

Methods of fabricating a semiconductor IC having a hardened shallow trench isolation (STI)

In order to produce insulator structures (), insulator trenches () with aspect ratios of greater than 4:1 are introduced into a semiconductor substrate () from a substrate surface () and filled with an insulator filling (). The insulator filling () is formed from a plurality of portions () which are deposited successively in situ in an HDP/CVD process chamber in the course of an HDP/CVD deposition process. A main layer () is provided made from fluorine-doped silicon oxide with good filling properties. A barrier layer () is formed directly before the deposition of the main layer (), said barrier layer preventing an outgassing of the fluorine from the fluorine-doped silicon oxide (), an interaction of the fluorine with the semiconductor substrate () and a formation of defect areas () with oxide of low quality in the area of the insulator filling (). The barrier () makes it possible to form nondegrading p-channel transistors () in the area of the substrate surface (). An additional layer () and a termination layer () respectively effect an adaptation and linking of the main layer () and of the barrier layer () to preceeding and succeeding process steps.

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Dresden, Germany

Joerg Radecker