Advanced Micro Devices Corporation

Globalfoundries Inc.

Joerg Hohage

Hartmut Ruelke

Ralf Richter

Matthias Lehr

Kai Frohberg

Volker Kahlert

Michael Finken

Thomas Werner

Minh Van Ngo

Martin Mazur

Matthias Schaller

Heike Salz

Lothar Mergili

Andy C Wei

Lu You

Manfred Horstmann

Richard J Huang

Frank Feustel

Frank G Kuechenmeister

Robert A Huertas

Axel Preusse

Martin Gerhardt

Holger S Schuehrer

Frank Koschinsky

Massud Aminpur

Frank Seliger

Oliver Aubel

Andreas Ott

Tobias Letz

Volker Grimm

Frank Mauersberger

Sven Mueller

Volker Jaschke

Ulrich Mayer

Jana Schlott

Michael Kiene

Jochen Klais

Richter Ralf

By determining at least one surface characteristic of a passivation layer stack used for forming a bump structure, the situation after the deposition and patterning of a terminal metal layer stack may be 'simulated,' thereby providing the potential for using well-established bump manufacturing techniques while nevertheless significantly reducing process complexity by omitting the deposition and patterning of the terminal metal layer stack.

Technique for forming a passivation layer without a terminal metal

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.

Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress

A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material

In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately 'encapsulated' by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level.

Non-insulating stressed material layers in a contact level of semiconductor devices

In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.

Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer

A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based deposition of silicon based dielectric barrier material. The thermal-chemical cleaning process is performed in the absence of any plasma ambient.

Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment

During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.

Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices

In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools.

Reduced wafer warpage in semiconductors by stress engineering in the metallization system

By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.

Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials

By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.

Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device

By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices.

Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device

By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.

Arc layer having a reduced flaking tendency and a method of manufacturing the same

By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.

Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device

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Dresden, Germany

Joerg Hohage