Cadence Design Systems, Inc.

Joel R Philips

Igor Keller

Jijun Chen

In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (q) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (I) for input waveforms from the timing library; determining timing values (d) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (q) by minimizing a residual of a delay equation.

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Oakland, CA, United States of America

Joel R Philips