Micron Technology Incorporated

Honeywell International Inc.

Round Rock Research, LLC

Joel A Drewes

Theodore Zhu

Durai Vishak Nirmal Ramaswamy

Shaoping Li

Romney R Katti

Donald L Yates

Eric Blomiley

Timothy J Vogt

William L Larson

Lonny L Berg

Harry Liu

Yong Lu

James G Deak

Anthony Arrott

Cem Basceri

Mark E Tuttle

Eugene P Marsh

Ross S Dando

Demetrius Sarigiannis

Jaydeb Goswami

Terry Gafron

William Frank Witcraft

Danny Dynka

The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

System having improved surface planarity for bit material deposition

The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.

Memory constructions comprising magnetic materials

Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.

Methods of titanium deposition

The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR)(NRR), wherein each R, R, and Ris independently hydrogen or an organic group, with the proviso that at least one of R, R, and Ris a silicon-containing organic group. Such systems and methods can be useful for depositing tantalum silicon nitride layers on substrates.

Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds

Assemblies comprising magnetic elements and magnetic barrier or shielding

Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.

Method for production of MRAM elements

An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.

System and method for reducing shorting in memory cells

The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having dispersers between lamps and a substrate. The invention also includes optical methods for utilization within a deposition apparatus for assessing the alignment of a substrate within the apparatus and/or for assessing the thickness of a layer of material deposited within the apparatus.

Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses

The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of titanium halide precursor and one or more reductants to form the titanium-containing material. For instance, the invention can utilize alternating cycles of titanium tetrachloride and activated hydrogen to form titanium silicide on a surface of a silicon-containing substrate.

Methods of forming titanium-containing materials

Assemblies comprising magnetic elements and magnetic barrier or shielding at least partially around the magnetic elements

In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.

Substrate susceptors for receiving semiconductor substrates to be deposited upon

The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Pseudo SOI substrate and associated semiconductor devices

A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Growing community of inventors

Boise, ID, United States of America

Joel A Drewes