Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Job Ha

Sun Woo Yun

Mi Jin Park

Sung Man Pang

Jae Hoon Park

Young Hoon Kwak

Eun Jung Jo

Kyu Hwan Oh

Ji Eun Park

Chang Seob Hong

Seung Wook Park

Kwang Soo Kim

Tae Hoon Kim

Sung Hyun Kim

In Wha Jeong

Seog Moon Choi

Suk Ho Lee

Sunghyun Kim

Bum Seok Suh

Jin Suk Son

Kee Ju Um

Chang Jae Heo

Young Ho Sohn

Si Joong Yang

Ju Pyo Hong

Hyo Jin Lee

Joon Hyung Cho

Jun Ho Lee

Jina Jeung

Ji Na Jeung

Suk Ho Kee

Jang Man Kim

A semiconductor package includes a frame having first and second surfaces opposite to each other, having first and second through holes, and including a wiring structure connecting the first and second surfaces, a connection structure disposed on the first surface of the frame and having a redistribution layer connected to the wiring structure, a first semiconductor chip having a first surface having a first pad connected to the redistribution layer and a second surface opposite to the first surface and having a second pad, a second semiconductor chip having an active surface having a connection pad connected to the redistribution layer and an inactive surface opposite to the active surface, an encapsulant encapsulating the first and second semiconductor chips, and a wiring layer connected to the second pad of the first semiconductor chip and the wiring structure.

Semiconductor package

A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.

A semiconductor package includes an organic frame having first and second surfaces opposing each other, having a cavity, and having a wiring structure connecting the first and second surfaces, a connection structure disposed on the first surface of the organic frame and having a first redistribution layer connected to the wiring structure, at least one inorganic interposer having first and second surfaces, and having an interconnection wiring connecting the first and second surfaces of the at least one inorganic interposer to each other, an encapsulant encapsulating at least a portion of the at least one inorganic interposer, an insulating layer disposed on the second surface of the organic frame and the second surface of the at least one inorganic interposer, a second redistribution layer having portions provided as a plurality of pads, and at least one semiconductor chip having connection electrodes respectively connected to the plurality of pads.

Hybrid interposer and semiconductor package including the same

Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.

All-in-one power semiconductor module

Disclosed herein are a power module package and a method of manufacturing the same. The power module package includes first and second semiconductor devices mounted on sides of first and second lead frames, ends of which are separated from each other, respectively, a support pin corresponding to a mounting position of the first semiconductor device and formed adjacent to a lower portion of the first lead frame, and a molding portion formed to cover portions of the first and second lead frames and the first and second semiconductor devices.

Power module package and method of manufacturing the same

Semiconductor device

Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

Wafer level device package with sealing line having electroconductive pattern and method of packaging the same

Growing community of inventors

Suwon-si, South Korea

Job Ha