Qualcomm Incorporated

Joan Rey Villarba Buot

Hong Bok We

Aniket Patil

Kuiwon Kang

Zhijie Wang

Michelle Yejin Kim

Terence Cheung

Joonsuk Park

Ching-Liou Huang

Karthikeyan Dhandapani

Jialing Tong

A substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength. In one aspect, a substrate comprises a core layer. The core layer comprises a metal core, the metal core having a first surface and a second surface opposite the first surface. The core layer further comprises a first insulation layer on the first surface and a second insulation layer on the second surface. The substrate further comprises a first metallization structure adjacent to the first insulation layer and a second metallization structure adjacent to the second insulation layer. The metal core provides electrical shielding of signals/power routed through the metal core for noise coupling reduction allowing a higher density of signal and power paths to be supported in substrate, while also strengthening structural integrity to prevent or reduce warpage in the IC package.

Substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength, and related IC packages and fabrication methods

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods. The IC package includes a first semiconductor die ('first die') and a first electronic device each coupled to a package substrate. To provide signal routing paths between the first die and the first electronic device, the IC package includes a wire bond channel that includes wire bonds coupled between first and second metal pads coupled to the respective first die and first electronic device to provide signal routing paths between the first die and first electronic device. The wire bonds extend outside of the package substrate in a vertical direction. The wire bond channel may be able to support more direct signal routing paths between the first die and the first electronic device without having to route such signal routing paths around a KoZ in the package substrate.

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods

Integrated circuit (IC) packages employing a supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer to reduce metal density mismatch, and related fabrication methods. An IC package includes a semiconductor die ('die') electrically coupled to a package substrate. The package substrate includes a die-side ETS metallization layer adjacent to and coupled to the die. To reduce or avoid metal density mismatch between the die-side ETS metallization layer and another metallization layer(s) in the package substrate, a supplemental metal layer with additional metal interconnects is disposed adjacent to the die-side ETS metallization layer. The additional metal interconnects are coupled in a vertical direction to the embedded metal traces in the die-side ETS metallization layer to increase metal density of die-side metal interconnects formed by the additional metal interconnects coupled to the embedded metal traces in the die-side ETS metallization layer.

Integrated circuit (IC) packages employing supplemental metal layer coupled to embedded metal traces in a die-side embedded trace substrate (ETS) layer, and related fabrication methods

Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.

Recess structure for padless stack via

Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.

Integrated circuit (IC) package employing added metal for embedded metal traces in ETS-based substrate for reduced signal path impedance, and related fabrication methods

Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include least a first metallization layer includes a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

Circular bond finger pad

A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

Substrate comprising interconnects in a core layer configured for skew matching

Terminal connection routing on top of a substrate surface connects to component terminals to and from PMIC devices and provides a novel structure to connect surface mount technology (SMT) passive device terminals on an SMT layer (such as a Cu bar mesh) that uses the 3D space available near to components to lower resistance/lower inductive path and provides a shorter path, SIP form factor reduction, a component placement density increase, creates an additional PDN layer for connectivity and, if the routing is encapsulated in a mold, protects the metal in the connection from oxidation. Methods are presented for providing a substrate, attaching a first device to a first surface of the substrate near a center of the substrate, attaching a second device to the first surface of the substrate near an edge of the substrate, and connecting a connection located on the first surface of the substrate between the first device and the second device.

Terminal connection routing and method the same

Multi-sided antenna modules employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related antenna module fabrication methods. The multi-sided antenna module includes an integrated circuit (IC) die(s) disposed on a first side of the package substrate. The multi-sided antenna module further includes first and second substrate antenna layers disposed on respective first and second sides of the package substrate. The first substrate antenna layer includes a first antenna(s) disposed on the first side of the package substrate adjacent to the IC die(s). The second substrate antenna layer includes a second antenna(s) disposed on the second side of the package substrate opposite of the first side of the package substrate. In this manner, the multi-sided antenna module, including antennas on multiple sides of the package substrate, provides antenna coverage that extends from both sides of the package substrate to provide multiple directions of coverage.

Multi-sided antenna module employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related fabrication methods

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods. To facilitate providing a reduced thickness substrate in the IC package to reduce overall height of the IC package while supporting higher density input/output (I/O) connections, a package substrate in the IC package includes a double side ETS. A double side ETS includes two (2) adjacent ETS metallization layers that both include metal traces embedded in an insulating layer. The embedded metal traces in the ETS metallization layers of the double side ETS can be electrically coupled to each other through vertical interconnect accesses (vias) (e.g., metal pillars, metal posts) to provide signal routing paths between embedded metal traces in the ETS metallization layers.

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods

A device comprising a first substrate comprising a first plurality of pillar interconnects; a second substrate comprising a second plurality of pillar interconnects, wherein the second plurality of pillar interconnects is coupled to the first plurality of pillar interconnects through a plurality of solder interconnects; a passive component located between the first substrate and the second substrate; and an integrated device coupled to the first substrate.

Package comprising passive component between substrates for improved power distribution network (PDN) performance

Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

Semi-embedded trace structure with partially buried traces

An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

Integrated circuit (IC) package with stacked die wire bond connections, and related methods

A device comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated device coupled to the first substrate. The second package includes a second substrate and a second integrated device coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

Package comprising inter-substrate gradient interconnect structure

A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.

Growing community of inventors

Escondido, CA, United States of America

Joan Rey Villarba Buot