Siemens Aktiengesellschaft

Infineon Technologies Ag

International Business Machines Corporation

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Siemens Aktiegensellschaft

Joachim Hoepfner

Martin Schrems

Jack Allan Mandelman

Helmut Horst Tews

Reinhard J Stengl

Hua Shen

Herbert Schaefer

Klaus-Dieter Morhard

Hans-Peter Zwicknagl

Kai Wurster

Carl John Radens

Walter Hartner

Frank S Hintermaier

Volker Weinrich

Brian S Lee

Guenther Schindler

Rolf-Peter Vollertsen

Spyridon Gisdakis

Lothar Schleicher

Hans Cerva

Franz Winterauer

A method for producing a ferroelectric layer includes preparing a substrate, applying a layer of material, which will be subsequently converted into the ferroelectric layer, and changing the material into the ferroelectric layer by applying an outer electrical field aligned with the direction desired in the ferroelectric material and heat treating the material. By providing a first noble metal electrode on the surface before applying the material that is to become the ferroelectric layer and then subsequently forming a second noble metal electrode on the ferroelectric layer, a ferroelectric storage capacitor can be formed. If the substrate is provided with memory cells, which include at least one transistor for each cell and the above-mentioned ferroelectric storage capacitors, a ferroelectric memory arrangement can be produced.

Method for producing a ferroelectric layer

A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next step is forming at least one connection, in particular a polysilicon connection. The next step is exposing the at least one connection from the wafer front surface. The next step is applying a protective layer, in particular a silicon nitride protective layer, to the wafer front surface. The next step is treating the wafer front surface by a chemical mechanical polishing (CMP) step, with the result that the at least one connection is made accessible again.

Method for fabricating an integrated semiconductor product

Plasma doping for DRAM with deep trenches and hemispherical grains

A method for reducing a capacitance formed on a silicon substrate includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method includes the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen includes forming hydrogen atoms in the surface with concentrations of 10 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are introduced by baking in hydrogen at a temperature of 950&deg; C. to 1100&deg; C. and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.

Low leakage, low capacitance isolation material

A contact between a polycrystalline silicon structure and a monocrystalline silicon region is produced by doping the silicon structure in amorphous or polycrystalline form and/or doping the monocrystalline silicon region with a dopant, in particular with oxygen, in such a concentration that a solubility limit is exceeded. In a subsequent heat treatment, dopant precipitations are formed which either control grain growth in the polycrystalline silicon layer or prevent a propagation of crystal faults into a substrate in the monocrystalline silicon region. Such a contact can be used, in particular, as a buried strap in a DRAM trench cell.

Contact between a monocrystalline silicon region and a polycrystalline silicon structure and method for producing such a contact

The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.

Stack capacitor with improved plug conductivity

A trench capacitor, in accordance with the present invention, includes a trench formed in a substrate. The trench has a buried plate formed adjacent to a lower portion of the trench. A dielectric collar is formed along vertical sidewalls of the trench. A node diffusion region is formed adjacent to the trench for connecting to a storage node in the trench. A dopant region is formed laterally outward from the trench and adjacent to the collar, and the dopant region includes a profile having a lower portion extending further laterally outward from the trench than an upper portion of the profile wherein operation of a parasitic transistor formed adjacent to the trench between the node diffusion and the buried plate is disrupted by the dopant region. Methods for forming the dopant region are also disclosed and claimed.

Method for fabricating a trench capacitor

A method for producing a polycrystalline silicon structure and a polycrystalline silicon layer to be produced by the method of first forming a primary silicon structure in an amorphous or polycrystalline form, and doping the structure with a dopant, in particular with oxygen, in a concentration exceeding the solubility limit. In a subsequent heat treatment, dopant precipitations are formed which control grain growth in a secondary structure being produced. Such a contact polycrystalline silicon structure can be used, in particular, as a connection of a monocrystalline silicon region.

Method for producing a polycrystalline silicon structure and

Method of forming stack capacitor with improved plug conductivity

A bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

Bottle-shaped trench capacitor with epi buried layer

A method for forming a trench capacitor in a substrate, including a buried plate of the trench capacitor, is disclosed. The method includes forming a trench within the substrate. The trench has a trench interior surface. The method further includes forming an oxide collar within the trench. The oxide collar covers a first portion of the trench interior surface, leaving a second portion of the trench interior surface uncovered with the oxide collar. There is also included doping the second portion of the trench interior surface with a first dopant using a plasma-enhanced doping process. The plasma-enhanced doping process being configured to cause the first dopant to diffuse into the second portion substantially without depositing an additional layer on the trench interior surface. Additionally, there is included driving the first dopant into the substrate using a high temperature process to form the buried plate.

Method for forming trench capacitors in an integrated circuit

A trench capacitor with an epi layer in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

Trench capacitor with epi buried layer

A planar heterobipolar transistor and its methods for manufacture provide that the transistor has the base-emitter region separated from the collector terminal by a collector parting trench and the parting trench structure may be used to separate the transistor from adjoining function components.

Method of making planar heterobipolar transistor having trenched

Method for manufacturing a self-aligned emitter-base complex whereby a sequence of epitaxial layers, which corresponds to the optimal base-emitter layer sequence in the re-etched part of the heterobipolar transistor is grown. Subsequently, the base implantation is introduced using a dummy-emitter as a mask. Using a dielectric mask covering the region not covered by the dummy-emitter, after the removal of the dummy-emitter the emitter contact layers are selectively grown in its region. The contacting is then provided.

Manufacturing method for a self-aligned emitter-base-complex for

In an apparatus for curing semiconductor wafers implementing same is provided. Pursuant to the method, semiconductor wafers, for example, GaAs, are cured in a reaction tube under a protective gas atmosphere of, for example, a mixture of N.sub.2 and AsH.sub.3. The reaction tube is initially heated to a base temperature at which the curing process is not initiated and at which no wall coatings occur. Given semiconductor wafers of compound semiconductors such as, for axample, GaAs, the protective atmosphere contains a compound of the more volatile element, for example, AsH.sub.3, that decomposes at the base temperature and forms an over-pressure of the more volatile element. The semiconductor wafer is heated to the curing temperature with a selective heater, for example a lamp, and is exposed to the curing temperature for 5 through 20 seconds.

Growing community of inventors

Planegg, Germany

Joachim Hoepfner