Infineon Technologies Ag

Infineon Technologies Flash Gmbh & Co. Kg

Qimonda Ag

Globalfoundries Inc.

Infineon Technology Ag

Joachim Deppe

Christoph Ludwig

Christoph Kleint

Jens-Uwe Sachse

Josef Willer

Ricardo Pablo Mikalo

Dominik Olligs

Mark Isler

Jan-Malte Schley

Mathias Krause

David Pritchard

Günther Wein

Eike Ruttkowski

Ralf Richter

A semiconductor device structure includes a semiconductor substrate with an active region provided therein, a gate structure, a dummy gate structure and two contact regions provided in the active region for forming source and drain regions. The gate structure and the dummy gate structure are formed on the semiconductor substrate so as to partially overlie the active region, and one of the contact regions is located at one side of the dummy gate structure. The semiconductor device structure includes a contact structure contacting one of the contact regions and the dummy gate for connecting this contact region and the dummy gate to one of a Vdd rail and a Vss rail. The active region has an extension portion protruding laterally away from the active region relative to the other contact region, where the contact structure is located over the extension portion.

Semiconductor device structure including active region having an extension portion

A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.

Integrated circuit including structures arranged at different densities and method of forming the same

A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.

Memory device, a non-volatile semiconductor memory device and a method of forming a memory device

A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories

A non-volatile semiconductor memory () comprising a semiconductor substrate () and a plurality of memory cells () and methods for manufacturing such a memory is provided. Each memory cell () comprises a charge-trapping element (), a gate stack (), nitride spacers () and electrically insulating elements (). The charge-trapping element () is arranged on the semiconductor substrate () and comprises a nitride layer () sandwiched between a bottom oxide layer () and a top oxide layer (), the charge-trapping element () having two lateral sidewalls () opposed to one another. The gate stack () is arranged on top of the charge-trapping element (), the gate stack having two lateral sidewalls () opposing one another. The electrically insulating elements () are disposed at opposing sidewalls () of the charge-trapping element () and cover the sidewalls () of the charge-trapping element (). The nitride spacers () cover the electrically insulating elements () and are arranged on opposing sidewalls () of the gate stack () and on the electrically insulating elements ().

Semiconductor memory

In the method, trenches () are etched and, in between, bit lines () are in each case arranged on doped source drain/regions (). Dopant is introduced into the bottoms of the trenches () in order to form doped regions (), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes () are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines () to an extent such that the doped regions () are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.

Method for fabricating an NROM memory cell arrangement

A trench () is fabricated in a silicon body (). The walls () of the trench are provided with a nitrogen implantation (). An oxide layer between the source/drain regions () and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

SONOS memory cells and arrays and method of forming the same

In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.

Memory cell

An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer () and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n-type well () for the source/drain regions, the bit line layer () is patterned using an etching stop layer () arranged on the semiconductor body ().

Method for fabricating NROM memory cells with trench transistors

In the method, trenches are etched and, in between, bit lines () are in each case arranged on doped source/drain regions (). Storage layers () are applied and gate electrodes () are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer () is reached, and afterward a polysilicon layer (), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

Method for fabricating an NROM memory cell array

In a charge trapping memory architecture for virtual ground with interconnects () that are present parallel to the word lines () and STI isolations () that are present parallel to the bit lines (), provision is made of STI isolations () that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines () may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.

Semiconductor memory having charge trapping memory cells

Electrically conductive material is introduced into interspaces between the word lines () and is partially removed using a mask () in such a way that residual portions () of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.

Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate

A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.

Method for fabricating semiconductor memories with charge trapping memory cells

Outside a memory cell field, bit-line contacts are provided on the top bit lines and additional bit-line contacts are provided on the lower bit lines and are each connected in an electrically conductive way to a metallization layer provided for wiring. The bit-line contacts for the upper bit lines and the additional bit-line contacts for the lower bit lines are formed on opposite sides of the memory cell field and portions of the isolation trenches are present between the additional bit-line contacts.

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Dresden, Germany

Joachim Deppe