Changxin Memory Technologies, Inc.

Jo-lan Chin

Deyuan Xiao

Semyeong Jang

Joonsuk Moon

Minki Hong

Kyongtaek Lee

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate, a gate structure and a dielectric layer. Herein, the substrate includes discrete semiconductor pillars. The semiconductor pillars are arranged at the top of the substrate and extend in a vertical direction. The substrate further includes a capacitor structure located at the top of the semiconductor pillar. The gate structure is arranged at the middle area of the semiconductor pillar and surrounds the semiconductor pillar. The dielectric layer is located between the gate structure and the semiconductor pillar, and covers the sidewall of the semiconductor pillar.

Semiconductor structure and method for manufacturing same

A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.

Semiconductor structure with semiconductor pillars and method for manufacturing same

A semiconductor structure and a method for manufacturing a semiconductor structure are provided, which relate to the technical field of semiconductors. The semiconductor structure includes a substrate and a plurality of first conductive layers. The substrate includes a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction. A plurality of active pillars are provided between the plurality of first trenches and the plurality of second trenches. The first direction intersects with the second direction. Each of the plurality of first conductive layers is arranged on each of sidewalls, which are arrayed in the first direction, of a respective one of the plurality of active pillars.

Semiconductor structure and method for manufacturing semiconductor structure

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes: a substrate, a dielectric layer, a first gate structure and a second gate structure. The substrate includes discrete semiconductors arranged at a top of the substrate and extending in a vertical direction. The first gate structure is arranged in a first region of the semiconductor pillar and surrounds the semiconductor pillar. The second gate structure is arranged in a second region of the semiconductor pillar and includes a ring structure and at least one bridge structure. The ring structure surrounds the semiconductor pillar, and the at least one bridge structure penetrates through the semiconductor pillar and extends to an inner wall of the ring structure in a penetrating direction. The dielectric layer is located between the first gate structure and the semiconductor pillar, and between the second gate structure and the semiconductor pillar.

Vertical gate all around transistor having dual gate structures

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base including bit lines arranged at intervals and extending along a first direction, and a semiconductor channel located on partial top surfaces of the bit lines, where along a direction from the bit line to the semiconductor channel, the semiconductor channel includes a first region, a second region, and a third region that are arranged sequentially; a dielectric layer located between adjacent two of the bit lines and on a sidewall of the semiconductor channel; a gate structure at least surrounding the dielectric layer in the second region and extending along a second direction, where the first direction is different from the second direction; an electrical connection layer covering a top surface of the third region and extending to a partial sidewall of the semiconductor channel.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes: a base, including bit lines extending in a first direction and semiconductor channels on the bit lines that are respectively arranged at intervals, in which a semiconductor channel includes a first region, a second region and a third region arranged in sequence; a dielectric layer, located between two adjacent ones of the bit lines and on a surface of the semiconductor channel; a first gate layer, surrounding the dielectric layer of the second region and extending in a second direction; a second gate layer, surrounding the dielectric layer of the third region, which is spaced apart from the first gate layer in the direction perpendicular to the top surface of the bit line; and an insulation layer, located between the adjacent semiconductor channels on the same bit line and isolating the first gate layers and the second gate layers on the adjacent dielectric layers.

A semiconductor structure includes a base, a dielectric layer, a gate structure, and a covering layer. The base includes discrete semiconductor pillars. The semiconductor pillars are disposed at the top of the base and extend in a vertical direction. The dielectric layer covers the sidewall of the semiconductor pillar. The gate structure is disposed in the middle area of the semiconductor pillar. The gate structure includes a gate-all-around structure, the gate-all-around surrounding the semiconductor pillar. A first part of the dielectric layer is disposed between the gate structures and the semiconductor pillars. The covering layer covers the top of the semiconductor pillar and part of the sidewall close to the top. The material of the covering layer includes a boron-containing compound.

Semiconductor structure and method for manufacturing the same

Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the present disclosure includes: providing a substrate, the substrate being provided with first trenches arranged in a same direction; forming protective layers on side walls of the first trenches; forming second trenches at bottoms of the first trenches, the second trenches being wider than the first trenches; forming first spacers on side walls of the second trenches to reduce opening sizes of the second trenches; filling the first trenches and the second trenches to form second spacers, and forming voids in the second trenches; forming third trenches in the substrate, the third trenches being perpendicular to the first trenches; and forming bit lines in the third trenches.

Method for fabricating semiconductor structure and semiconductor structure

Embodiments relate to a semiconductor structure and a fabrication method. The method includes: providing a substrate, where a first trench is formed in the substrate; forming a first dielectric layer and a protective material layer in the first trench, where the first dielectric layer is positioned between the protective material layer and the substrate, and an upper surface of the first dielectric layer is lower than an upper surface of the substrate, to expose a portion of a side wall of the first trench; forming a second dielectric layer on the exposed side wall of the first trench; and filling the second trench to form a work function structure, where the work function structure includes a first work function layer and a second work function layer, where the second work function layer is positioned on an upper surface of the first work function layer.

Semiconductor structure and fabrication method thereof

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, where the base is provided with an array region and a peripheral region, the array region is provided with vertical transistor structures, the vertical transistor structures are arranged in an array in the array region, and the peripheral region surrounds the array region; a first gate layer surrounding the vertical transistor structure and extending along a first direction; a second gate layer surrounding the vertical transistor structure and extending along the first direction, where the second gate layer and the first gate layer surround a same vertical transistor structure, are disposed at intervals, and both extend to the peripheral region; and an electrical connection structure located in the peripheral region and electrically connected to the first gate layer and the second gate layer.

A semiconductor structure and a fabricating method are provided. The semiconductor structure includes a substrate, active pillars, gate structures, a metal silicide layer, and a spacer. The active pillars are positioned on the substrate and are arranged in an array, and the active pillars extend along a direction perpendicular to the substrate. The gate structures are arranged at intervals along a first direction, and the gate structures are arranged surrounding a part of the active pillars. The metal silicide layer is positioned on a top surface of the active pillar, and a projection of the metal silicide layer on the substrate is overlapped with a projection of the top surface of the active pillar on the substrate. The spacer is positioned between adjacent gate structures and adjacent active pillars, and a height of the spacer is higher than a height of a top surface of the metal silicide layer.

Method for fabricating semiconductor device and semiconductor device

A semiconductor structure includes: a base including bit lines arranged at intervals and semiconductor channels arranged at intervals, bit lines extending in first direction, semiconductor channels being located at part of top surfaces of bit lines, each semiconductor channel including first area, second area, and third area arranged successively in a direction perpendicular to top surfaces of bit lines; dielectric layers located between adjacent bit lines and located on side walls of semiconductor channels; gate electrodes surrounding dielectric layers in second area and extending in second direction; metal semiconductor compound layers located on top surfaces of semiconductor channels; diffusion barrier layers at least surrounding side walls of metal semiconductor compound layers; and insulating layers located between adjacent semiconductor channels on same bit line and isolating gate electrodes and diffusion barrier layers on each dielectric layer from gate electrodes and diffusion barrier layers on dielectric layers adjacent to each dielectric layer.

A method for determining a contour of a semiconductor structure is disclosed, which includes: acquiring a best inclination angle of an electron beam; irradiating a sidewall of the semiconductor structure with the electron beam at the best inclination angle, to obtain a measured width of an orthographic projection of the sidewall of the semiconductor structure within a plane perpendicular to an incidence direction of the electron beam; and determining whether a bottom of the semiconductor structure is necked based on the measured width.

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Hefei, China

Jo-lan Chin