United Microelectronics Corp.

Jiunn-Hsiung Liao

Yu-Tsung Lai

Pei-Yu Chou

Chih-Wei Kuo

Feng-Yi Chang

Shin-Chi Chen

Chieh-Te Chen

Guang-Yaw Hwang

Shih-Fang Tzou

Yi-Po Lin

Chih-Wen Feng

Ying-Chih Lin

Shang-Yuan Tsai

Jyh-Cherng Yau

Chien-Ting Lin

Chun-Hsien Lin

Shui-Yen Lu

Po-Jui Liao

Shao-Hua Hsu

Tsung-Lung Tsai

Meng-Jun Wang

Chan-Lon Yang

Po-Chao Tsao

Hsuan-Hsu Chen

Tai-Cheng Hou

Lung-En Kuo

Li-Chiang Chen

Ching-Pin Hsu

Hung-Ling Shih

Chang-Hsiao Lee

Chia-Wen Liang

Chun-Jen Huang

Min-Chieh Yang

Yeng-Peng Wang

Chin-Cheng Chien

Chiu-Hsien Yeh

Ming-Tsung Chen

Ling-Chun Chou

I-Chang Wang

Shin-Chuan Huang

Yi-Hsing Chen

Yi-Wei Tseng

Chang-Chi Huang

Ming-Da Hsieh

Wen-Chou Tsai

Pau-Chung Lin

Teng-Chun Tsai

Chun-Lung Chen

Shih-Wei Sun

Hsin-Yu Chen

Kun-Yuan Liao

Wen-Han Hung

Chia-Lin Lu

Chien-Ming Lai

Chia-Chang Hsu

Che-Hua Hsu

Zhi-Cheng Lee

Yu-Ru Yang

Wei-Hang Huang

Yi-Wen Chen

Cheng-Guo Chen

Wei-Hao Huang

Jie-Ning Yang

Tong-Jyun Huang

Ying-Tsung Chen

Chun-Ting Yeh

Ting-Hsiang Huang

Ching-Chung Chen

Shih-Chun Tsai

Jung-Tsung Tseng

Cheng-Ming Weng

Miao-Chun Lin

Cheng-Yu Ma

Chuan-Kai Wang

Kai-Teng Cheng

Feng-Yih Chang

Meng-Chun Lee

Chieh-Ju Wang

Kai-Siang Neo

Mei-Chi Wang

Wei-Cheng Yang

Kevin C K Wang

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a first spacer and a second spacer around the first MTJ, a third spacer and a fourth spacer around the second MTJ, a passivation layer between the second spacer and the third spacer as a top surface of the passivation layer includes a V-shape, and an ultra low-k (ULK) dielectric layer on the passivation layer and around the first MTJ and the second MTJ.

Semiconductor device and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.

A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.

Magnetic tunnel junction (MTJ) device

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.

A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.

Magnetic memory device and fabrication method thereof

A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.

A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.

Method for fabricating a semiconductor device

Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.

Manufacturing method for trench

A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.

Memory device including alignment mark trench

Conductor line structure

A method for fabricating a semiconductor device is provided including providing a substrate, on which a plurality of elements is formed. A first inter-dielectric layer is formed over the substrate, covering the elements. A first plug structure is formed in the first inter-dielectric layer, including performing a polishing process over the first inter-dielectric layer to have a dishing on top and extending from a sidewall of the first plug structure. A hard mask layer is formed to fill the dishing. A second inter-dielectric layer is formed over the hard mask layer. A second plug structure is formed in the second inter-dielectric layer to electrically contact the first plug structure, wherein the second plug structure has at least an edge portion extending on the hard mask layer.

Fabrication method and structure of semiconductor device with contact and plug

A method of forming a patterned mask layer includes the following steps. A plurality of support features is formed on a mask layer. A plurality of spacers is formed on side walls of the support features. A patterned protection layer is formed on the support features and top surfaces of the spacers. At least a part of side surfaces of the spacers are not covered by the patterned protection layer, and the patterned protection layer is formed in a process environment containing methane (CH). A trimming process is then performed to remove a part of each of the spacers. Tapered parts of the spacers may be removed by the trimming process before the step of etching the mask layer with the spacers as a mask, and the critical dimension uniformity of the patterned mask layer may be improved accordingly.

Method of forming patterned mask layer

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Tainan, Taiwan

Jiunn-Hsiung Liao