Taiwan Semiconductor Manufacturing Comp. Ltd.

Jiunn-Der Yang

Yuan-Chang Huang

Chao-Hsin Chang

Renn-Shyan Yeh

Wen-Chen Chang

Chaucer Chung

Chaucer Chnug

A method forming sidewall spacers on a semiconductor substrate without using the conventional plasma etching method is disclosed. In the method, a semiconductor substrate that has a gate structure formed on a top surface is first provided, followed by the deposition of a dielectric material layer on top of the semiconductor substrate. The substrate is then rotated to a rotational speed of at least 50 rpm, and an acid vapor is flown onto the substrate until the sidewall spacers are formed. The dielectric material layer for forming the sidewall spacers may be SiO , SiON or Si N . The acid vapor utilized may be formed from an acid of HF, H PO , H SO or HCl. In a preferred embodiment, the semiconductor substrate may be rotated to a rotational speed between about 100 rpm and about 150 rpm for a time period between about 10 sec. and about 20 sec.

Method for spin etching sidewall spacers by acid vapor

A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

Method and system for yield loss analysis by yield management system

A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.

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Hsinchu, Taiwan

Jiunn-Der Yang