Taiwan Semiconductor Manufacturing Comp. Ltd.

Jiung Wu

Wen-Chih Chiou

Chen-Hua Douglas Yu

Tsang-Jiuh Wu

Ku-Feng Yang

Ming-Tsu Chung

Hong-Ye Shih

Shin-Puu Jeng

Kuan-Liang Lai

Hsin-Yu Chen

Chen-Yu Tsai

Chih-Hang Tung

Jih-Churng Twu

Kuang-Wei Cheng

Fang Wen Tsai

Su-Chun Yang

Jiann Sheng Chang

Yi Chou Lai

A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

Die stacking structure, semiconductor package and formation method of the die stacking structure

An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Profile of through via protrusion in 3DIC interconnect

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

Self-alignment for redistribution layer

System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.

Reducing substrate warpage in semiconductor processing

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Kueishan Shiang, Taiwan

Jiung Wu