Taiwan Semiconductor Manufacturing Comp. Ltd.

Novatek Microelectronics Corp.

Jiun-Ting Chen

Szu-Wei Lu

Ying-Ching Shih

Chih-Wei Wu

Tsung-Fu Tsai

Chien-Yu Chen

Ting-Yu Yeh

Chen-Hsuan Tsai

Wei-Ying Tu

Chien-Chou Hung

Kuei-Chung Chang

Feng-Jung Kuo

Wen-Ping Chou

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Semiconductor package and manufacturing method thereof

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.

Chip package structure

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar over a first portion of the first chip structure and over a second portion of the second chip structure. A width of the anti-warpage bar overlapping the second portion of the second chip structure is greater than a width of the anti-warpage bar overlapping the first portion of the first chip structure.

A method for forming a chip package structure is provided. The method includes bonding a first chip structure and a second chip structure to a surface of a substrate. The first chip structure and the second chip structure are spaced apart from each other. There is a first gap between the first chip structure and the second chip structure. The method includes removing a first portion of the first chip structure and a second portion of the second chip structure to form a trench partially in the first chip structure and the second chip structure and partially over the first gap. The method includes forming an anti-warpage bar in the trench. The anti-warpage bar is over the first chip structure, the second chip structure, and the first gap.

Chip package structure and method for forming the same

A manufacturing method and a packaging process are provided. A package having a first die and a second die is provided. A circuit substrate having a first warpage level is provided. The package is mounted onto the circuit substrate and then heated under an elevated temperature to bond the package to the circuit substrate. The package heated under the elevated temperature is warped with a second warpage level, and the first warpage level is substantially in conformity with the second warpage level.

Packaging process and manufacturing method

A display driving apparatus including a receiver circuit, a detection circuit and a driving circuit is provided. The receiver circuit receives the video image data at a first rate. The detection circuit is coupled to the receiver circuit. The detection circuit detects whether the video image data is a static image, and determines whether the display driving apparatus enters a power saving mode based on a detecting result. The driving circuit is coupled to the receiver circuit. The driving circuit drives the display panel. In the power saving mode, the receiver circuit continuously receives the video image data at the first rate, and periodically masks a part of the video image data according to the detecting result and outputs an unmasked part of the video image data to the driving circuit. Furthermore, a display driving method adapted for the foregoing display driving apparatus is also provided.

Display driving apparatus and display driving method thereof

A display driving apparatus including a signal transmission interface, a timing control circuit and an image detection circuit is provided. The signal transmission interface is configured to receive video image data and output the video image data. The timing control circuit is configured to receive the video image data and drive a display panel based on the video image data. The image detection circuit determines whether the video image data is a static image and determines whether the display driving apparatus operates in a power-saving mode based on the determination result. Under the power-saving mode, the signal transmission interface masks a part of the video image data, so as not to output the masked video image data to the timing control circuit. Furthermore, a display driving method adapted for the foregoing display driving apparatus is also provided.

A driving signal generating device for staggering transition time of driving signals to prevent image crosstalk for a display device includes a receiving terminal, a first adjusting unit, a multiplexer, a second adjusting unit and a frame output controller. The receiving terminal receives a plurality of step grayscale waveforms. The first adjusting unit transforms the plurality of step grayscale waveforms into a plurality of initial grayscale waveforms and further adjusts widths of the plurality of initial grayscale waveforms according to a first predetermined value to generate a plurality of grayscale waveforms. The multiplexer selects a first grayscale waveform from the plurality of grayscale waveforms. The second adjusting unit then adjusts a width of the first grayscale waveform according to a second predetermined value to generate a second grayscale waveform. The frame output controller controls output of the first grayscale waveform and the second grayscale waveform.

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Hsinchu, Taiwan

Jiun-Ting Chen