Intel Corporation

Jiun-Ruey Chen

Matthew V Metz

Miriam Ruth Reshotko

Noriyuki Sato

Kevin Lai Lin

Mauro J Kobrinsky

Elijah V Karpov

Manish Chandhok

Hui Jae Yoo

Christopher J Jezewski

James M Blackwell

Ramanan Chebiam

Carl H Naylor

Tristan A Tronic

Nafees Kabir

Jeffery D Bielefeld

Michael Christenson

Scott Bruce Clendenning

John J Plombon

Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed on the vertically staggered interconnect lines. Cap material selectively deposited upon upper ones of the staggered interconnect lines limits over etch of the short vias while the tall vias are advanced toward lower ones of the staggered interconnect lines. The via openings of differing depth may be filled, for example with a single damascene metallization process that defines a co-planar top surface for all via metallization over the staggered, vertically spaced interconnect lines.

Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

Subtractively patterned interconnect structures for integrated circuits

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Hillsboro, OR, United States of America

Jiun-Ruey Chen