Macronix International Co., Ltd.

Other

Jiun-Ren Lai

Chien-Wei Chen

Chun-Yi Yang

Shi-Xian Chen

Gwen Chang

Ming-Chung Liang

Shin-Yi Tsai

A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Method of improving device resistance

A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides. Finally, the mask layer is stripped and then the spacing dielectric layer remains to form the electrical insulating layer on bit lines of the flash memory.

Method for forming an electrical insulating layer on bit lines of the flash memory

A method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits. In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer. The second polymer layer is used as an etching mask to define the conductive layer. Then, the second polymer layer is removed.

Pitch reduction in semiconductor fabrication

Structure of a memory device with buried bit line

A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the conductive layer, a polymer layer on top surfaces and sidewalls of each of the photoresist features, and a material layer on and around the photoresist features and the polymer layers. An upper portion of the material layer is removed such that upper surfaces of the photoresist features and the polymer layer are exposed, and a remaining portion of the material layer remains. The polymer layer is removed, and the photoresist features and the remaining portion of the material layer are used as etch masks to pattern the conductive layer, thereby producing a number of conductive features. The photoresist features and the remaining portion of the material layer are removed.

Method for reducing pitch between conductive features, and structure formed using the method

This invention relates to a method for fabricating a electrically insulating layer, more particularly, to the method for fabricating a electrically insulating layer by using the different etching rates in etching oxide and etching nitride. The present invention uses the way in different etching rates to etch oxide and nitride. When begin the etching process to fabricating the electrically insulating layer, the etching rate of oxide is higher than the etching rate of nitride. When the oxide layer contacts with the ending point which is situated between the oxide layer and the nitride layer or the nitride oxide layer, the etching rate of nitride is higher than the etching rate of oxide to form the flatter surface of the electrically insulating layer.

Method for fabricating electrically insulating layers

A method for fabricating a NROM is described, in which a bottom anti-reflective coating (BARC) and a photoresist pattern are sequentially formed on a substrate that has a charge trapping layer formed thereon. An etching process is then performed to pattern the BARC and the charge trapping layer with the photoresist pattern as a mask. The etching process is conducted in an etching chamber equipped with a source power supply and a bias power supply, which two have a power ratio of 1.5&tilde;3, while an etchant used therein is a gas plasma containing trifluoromethane (CHF ) and tetrafluoromethane (CF ). Thereafter, a buried drain is formed in the substrate, a buried drain oxide layer is formed on the buried drain, and then plural gates are formed on the substrate.

Method for fabricating NROM with ONO structure

A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

Growing community of inventors

Pingtung, Taiwan

Jiun-Ren Lai