Koninklijke Philips Corporation N.V.

Lumileds LLC

Jipu Lei

Stefano Schiaffino

Alexander H Nickel

Yajun Wei

Daniel Alexander Steigerwald

Salman Akram

Grigoriy Basin

Kwong-Hin Henry Choy

Mooi Guan Ng

Danel Alexander Steigerwald

Stefano Schiafino

A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

P&#x2014;N separation metal fill for flip chip LEDs

A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.

Sealed semiconductor light emitting device

A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

Reducing solder pad topology differences by planarization

A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.

LED having vertical contacts redistributed for flip chip mounting

P-n separation metal fill for flip chip LEDs

A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.

Method of separating a wafer of semiconductor devices

A device according to embodiments of the invention includes a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region and first and second metal contacts, wherein the first metal contact is in direct contact with the n-type region and the second metal contact is in direct contact with the p-type region. First and second metal layers are disposed on the first and second metal contacts, respectively. The first and second metal layers are sufficiently thick to mechanically support the semiconductor structure. A sidewall of one of the first and second metal layers comprises a three-dimensional feature.

Semiconductor light emitting device with thick metal layers

Thick metal pillars are formed upon light emitting dies while the dies are still on their supporting wafer. A molding compound is applied to fill the space between the pillars on each die, and contact pads are formed atop the pillars. The metal pillars provide electrical contact between the contact pads and the electrical contacts of each light emitting die. The metal pillars maybe formed upon an upper metal layer of each die, and this upper metal layer maybe patterned to provide connections to individual elements within the die.

Chip scale light emitting device with metal pillars in a molding compound formed at wafer level

A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-Type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.

LED having vertical contacts redistruted for flip chip mounting

A light emitting diode (LED) structure () has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer () is formed in the gap followed by filling the gap with a metal (). The metal is patterned to form stud bumps () that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

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San Jose, CA, United States of America

Jipu Lei