Texas Instruments Corporation

Micron Technology Incorporated

Jiong-Ping Lu

Ming-Jang Hwang

Wei-Yung Hsu

Haowen Bu

Qi-Zhong Hong

Ping Jiang

Donald S Miles

Shaofeng Yu

Lindsey H Hall

Changming Jin

Lance Stanford Robertson

Duofeng Yue

Clint Montgomery

Yaw S Obeng

Linlin Chen

Duane E Carter

Richard Allen Faust

Joe G Tran

Qing-Tang Jiang

ChangFeng F Xia

David Permana

Thomas Dyer Bonifield

Chih-Chen Cho

Freidoon Mehrad

Patricia Beauregard Smith

Ming J Hwang

Srinivasan Chakravarthi

Periannan Chidambaram

Sue E Crank

Jin Zhao

Juanita DeLoach

Yuqing Xu

Mark R Visokay

Amitava Chatterjee

Robert H Havemann

Brian Keith Kirkpatrick

William R McKee

Scott David Johnson

Rick L Wise

Kaiping Liu

Ting Yiu Tsui

Honglin Guo

Dirk N Anderson

Gregory Boyd Shinn

Wei William Lee

Song Zhao

Peijun Chen

Tz-Cheng Chiu

Andrew McKerrow

Rajesh Tiwari

Clinton L Montgomery

Jiejie Xu

Yoshimitsu Tamura

Jeff A West

Stephen W Russell

David Gonzalez, Jr

August J Fischer

Ralf B Willecke

Scott Alexander Johannesmeyer

Ching-Te Lin

Vivian Liu

Johan Weijtmans

Boyang Lin

Melissa M Hewson

Glenn J Tessmer

Xiaozhan Liu

Dick N Anderson

Richard A Faust, Jr

Thomas D Bonifiield

Jie-Jie Xu

Albert Cheng

Brock W Fairchild

Chris M Bowles

Yung Liu

Changfeng Xia

Changfeng F Xia

A low stress sacrificial cap layerhaving a silicon oxide liner film, a low stress silicon film, and a silicon nitride film Alternatively, a low stress sacrificial cap layerhaving a silicon oxide liner filmand a graded silicon nitride filmAlso, methodsfor fabricating a transistorhaving a low stress sacrificial cap layer

Low stress sacrificial cap layer

A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.

Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial SiGe

Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

Nickel silicide formation for semiconductor components

High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.

Method of forming capacitors

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layerlocated over a gate electrode layer, a capacitorlocated on the recrystallized polysilicon layer. The capacitor, in this embodiment, includes a first electrode, an insulatorlocated over the first electrode, and a second electrodelocated over the insulator

Capacitor formed on a recrystallized polysilicon layer

A low stress sacrificial cap layerhaving a silicon oxide liner film, a low stress silicon film, and a silicon nitride film. Alternatively, a low stress sacrificial cap layerhaving a silicon oxide liner filmand a graded silicon nitride film. Also, methodsfor fabricating a transistorhaving a low stress sacrificial cap layer

A method for making a transistorthat includes using a transition metal nitride layerand/or a SOG layerto protect the source/drain regionsfrom silicidation during the silicidation of the gate electrode. The SOG layeris planarized to expose the transition metal nitride layeror the gate electrodebefore the gate silicidation process. If a transition metal nitride layeris used, then it is removed from the top of the gate electrodebefore the full silicidation of the gate electrode

FUSI integration method using SOG as a sacrificial planarization layer

High-K dielectric materials and processes for manufacturing them

An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer. The method may include forming an interface layerover the semiconductor substrateand performing an anneal to create a silicideon the top surface of the gate electrode

Method for improving the thermal stability of silicide

A copper interconnect having a transition metal-silicon-nitride barrier (). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (). The copper () is then deposited over the transition metal-silicon-nitride barrier () with good adhesion.

In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliability

A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).

Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device

High-k dielectric materials and processes for manufacturing them

The present invention substantially removes dry etch residue from a dry plasma etch processprior to depositing a cobalt layeron silicon substrate and/or polysilicon material. Subsequently, one or more annealing processesare performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operationand then an extended cleaning operationthat includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operationis performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation

Process method to facilitate silicidation

Growing community of inventors

Richardson, TX, United States of America

Jiong-Ping Lu