Globalfoundries Inc.

Globalfoundries U.S. Inc.

Jinsheng Gao

Haigou Huang

Daniel J Jaeger

Michael Vincent Aquilino

Patrick D Carpenter

Huy Cao

Hui Zang

Xusheng Kevin Wu

Mitchell Rutkowski

Jinping Liu

Jessica M Dechene

Junsic Hong

Veeraraghavan S Basker

Chih-Chiang Chang

Christopher Nassar

Hong Yu

Huang Liu

Jiehui Shu

Haifeng Sheng

Pei Liu

Tai Fong Chao

One illustrative integrated circuit product disclosed herein includes a first final gate structure having a first end surface and a second final gate structure having a second end surface. In this embodiment, the integrated circuit product also includes an insulating gate separation structure positioned between the first and second final gate structures, wherein the first end surface contacts a first side surface of the insulating gate separation structure and the second end surface contacts a second side surface of the insulating gate separation structure. In this embodiment, the insulating gate separation structure has an inverted T-shaped cross-sectional configuration in at least one direction.

IC product comprising a novel insulating gate separation structure for transistor devices

The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

Cap structure

Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices

The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

Capping structure

At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device

One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure, removing the sacrificial gate structure to form a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

Methods of forming replacement gate structures on transistor devices

A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

Composite contact etch stop layer

At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.

Methods, apparatus and system for self-aligned metal hard masks

At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

Methods, apparatus and system for providing a pre-RMG replacement metal contact for a finFET device

At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A replacement metal gate (RMG) process is performed in the gate region. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

Methods, apparatus and system for replacement contact for a finFET device

Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Replacement contact cuts with an encapsulated low-K dielectric

One illustrative method disclosed herein includes, among other things, forming an initial patterned etch mask above a feature-formation etch mask, the initial patterned etch mask including a plurality of laterally spaced-apart features having a non-uniform spacing, and performing at least one first etching process to remove an entire axial length of at least one of the plurality of features so as to thereby form a modified final patterned etch mask comprised of a plurality of features with a uniform spacing that defines a feature-formation pattern. In this example, the method also includes performing at least one second etching process so as to form a patterned feature-formation etch mask comprising the feature-formation pattern and performing at least one third etching process so as to form a plurality of features in a first layer, the features being formed with the feature-formation pattern.

Methods of forming features on integrated circuit products

The disclosed methods may include depositing an amorphous carbon layer, a SiCN layer, and a TEOS layer; planarizing the semiconductor structure; performing a non-selective etch to remove the SiCN layer, the TEOS layer, and a portion of the amorphous carbon layer; and performing a selective etch of the amorphous carbon layer. The methods may reduce step height differences between first and second regions of the semiconductor structure.

Growing community of inventors

Clifton Park, NY, United States of America

Jinsheng Gao