International Business Machines Corporation

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Elpis Technologies Inc.

Jingyun Zhang

Choonghyun Lee

Alexander Reznicek

Takashi Ando

Pouya Hashemi

Ruilong Xie

Xin Miao

Chun Wing Yeung

Heng Wu

Robin Hsin Kuo Chao

Julien Frougier

Nicolas J Loubet

Kangguo Cheng

Bahman Hekmatshoartabari

Reinaldo Ariel Vega

Miaomiao Wang

Veeraraghavan S Basker

Andrew Mark Greene

Huimei Zhou

ChoongHyun Lee

Effendi Leobandung

Junli Wang

Dechao Guo

Hemanth Jagannathan

Ruqiang Bao

Kevin W Brew

Lan Yu

Adra Carr

Robin H Chao

Tian Shen

Robinhsinku Chao

Bruce Bennett Doris

Tenko Yamashita

Juntao Li

Peng Xu

Chen Zhang

Shogo Mochizuki

Shay Reboh

Jing Guo

Derrick Liu

Remi Coquand

Sagarika Mukesh

Liying Jiang

Clint Oteri

SangHoon Shin

Robin Hsin-Ku Chao

Carl John Radens

Zhenxing Bi

Ekmini Anuja De Silva

Su Chen Fan

Koji Watanabe

Xuefeng Liu

Muthumanickam Sankarapandian

Anthony I Chou

Indira P Seshadri

Charan V Surisetty

Pietro Montanini

Dimitri Houssameddine

Thamarai Selvi Devarajan

Siva Kanakasabapathy

Sung Dae Suk

Binglin Miao

A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

Gate stack quality for gate-all-around field-effect transistors

Embodiments are for vertical field effect transistors having different threshold voltages along the channel. A vertical fin having a vertical channel is formed, one end of the vertical channel including a doped layer, the doped layer causing a threshold voltage at the one end to be different from a remainder of the vertical channel. A source and a drain are formed each coupled to opposite ends of the vertical fin, gate material being formed on the vertical channel.

Vertical transport field effect transistors having different threshold voltages along the channel

Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

Hybrid gate cut for stacked transistors

A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.

Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor

A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

Multi-Vt nanosheet devices

A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.

Nanosheet device with tri-layer bottom dielectric isolation

A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

Metal gate patterning for logic and SRAM in nanosheet devices

Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion

A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first distance and having a first critical voltage. A second MTJ having a second distance and having a second critical voltage, wherein the first distance and the second distance are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.

Multi-state SOT-MRAM structure

In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Electrostatic discharge diode having dielectric isolation layer

A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

Three terminal phase change memory with self-aligned contacts

Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Replacement-channel fabrication of III-V nanosheet devices

A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Nanosheet transistor with ferroelectric region

Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.

Optimized contact resistance for stacked FET devices

Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

Planar devices with consistent base dielectric

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Albany, NY, United States of America

Jingyun Zhang