Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International Corp.

Jinghua Ni

Aileen Li

Eugene Wang

Fenglian Li

Jian Zhao

Lei Wu

Jianping Wang

Jingang Wu

David Han

A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate including a transistor and a dummy gate disposed on the transistor, removing the dummy gate on the transistor, performing treatment using hydrogen (H) on a surface of the semiconductor substrate, so as to remove residue materials left behind from the removal of the dummy gate, and forming a metal gate on the transistor.

Method of manufacturing a semiconductor device

A method for manufacturing a semiconductor device includes providing a substrate, a dielectric layer on the substrate, a first hard mask layer on the substrate, and a second hard mask layer on the first hard mask layer. The method also includes removing the first hard mask layer using a reactive gas that does not cause damage to the dielectric layer to improve the performance and yield of the semiconductor device.

Method for chemical mechanical polishing of high-K metal gate structures

A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming a first dielectric layer on a surface of the semiconductor substrate based on a first-type oxidation, and forming a high-K dielectric layer on a surface of the first dielectric layer. The method also includes performing a first thermal annealing process to remove the first dielectric layer between the semiconductor substrate and the high-K dielectric layer such that the high-K dielectric layer is on the surface of the semiconductor substrate. Further, the method includes performing a second thermal annealing process to form a second dielectric layer on the surface of the semiconductor substrate between the semiconductor substrate and the high-K dielectric layer, based on a second-type oxidation different from the first-type oxidation, such that high-K dielectric layer is on the second dielectric layer instead of the first dielectric layer.

High-K dielectric layer based semiconductor structures and fabrication process thereof

Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each of the protective layer and the high-K dielectric layer can be removed from the fuse region to expose the STI structure. A fuse layer can be formed on the exposed surface of the STI structure. A portion of the fuse layer, the remaining portion of the protective layer, and a remaining portion of the high-K dielectric layer outside of the fuse region can be removed from the semiconductor substrate to form a fuse structure.

Semiconductor structure and fabrication method

Various embodiments provide transistors and their fabrication methods. An exemplary method for forming a transistor includes removing a dummy gate to form a trench over a semiconductor substrate. A high-k dielectric layer can be conformally formed on surface of the trench and then be fluorinated to form a fluorinated high-k dielectric layer. A functional layer can be formed on the fluorinated high-k dielectric layer and a metal layer can be formed on the functional layer to fill the trench with the metal layer. Due to fluorination of the high-k dielectric layer, negative bias temperature instability of the formed transistor can be reduced and oxygen vacancies can be passivated to reduce positive bias temperature instability of the transistor.

Transistor device and fabrication method

A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining TiN layer, and a remaining TaN layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer.

Gate structure and manufacturing method thereof

A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K gate dielectric layer, a high-K gate dielectric protection layer containing nitrogen and a poly silicon dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the poly silicon dummy gate structure. Further, the method includes removing the poly silicon dummy gate to form a trench exposing the high-K gate dielectric protection layer containing nitrogen and performing a nitrogen treatment process to repair defects in the high-K gate dielectric protection layer containing nitrogen caused by removing the poly silicon dummy gate. Further, the method also includes forming a metal gate structure in the trench.

MOS transistors and fabrication method thereof

A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure.

Through silicon via packaging structures and fabrication method

A method and system for processing commonality of semiconductor devices. The method includes providing a first plurality of semiconductor devices, providing a second plurality of semiconductor devices, obtaining a first plurality of measured values corresponding to a characteristic associated with the first plurality of semiconductor devices, obtaining a second plurality of measured values corresponding to the characteristic associated with the second plurality of semiconductor devices, performing a first statistical analysis for the first plurality of measured values, determining a first statistical distribution, performing a second statistical analysis for the second plurality of measured values, and determining a second statistical distribution. Moreover, the method includes processing information associated with the first statistical distribution and the second statistical distribution, and determining an indicator. Also, the method includes processing information associated with the indicator, determining a confidence level, processing information associated with the confidence level, and determining whether the characteristic is stable.

Method and system for processing commonality of semiconductor devices

A method and system for processing commonality of semiconductor devices. The method includes providing a first plurality of semiconductor devices, providing a second plurality of semiconductor devices, obtaining a first plurality of measured values corresponding to a characteristic associated with the first plurality of semiconductor devices, and obtaining a second plurality of measured values corresponding to the characteristic associated with the second plurality of semiconductor devices. Additionally, the method includes performing a first statistical analysis, determining a first statistical distribution, performing a second statistical analysis, and determining a second statistical distribution. Moreover, the method includes processing information associated with the first statistical distribution and the second statistical distribution, and determining an indicator. Also, the method includes processing information associated with the indicator, determining a confidence level, processing information associated with the confidence level, and determining whether the characteristic is stable.

A method and system for processing stability of semiconductor devices. The method includes providing a first plurality of semiconductor devices, providing a second plurality of semiconductor devices, obtaining a first plurality of measured values corresponding to a characteristic, and obtaining a second plurality of measured values corresponding to the characteristic. Additionally, the method includes performing a first statistical analysis for the first plurality of measured values, determining a first statistical distribution, performing a second statistical analysis for the second plurality of measured values, and determining a second statistical distribution. Moreover, the method includes processing information associated with the first statistical distribution and the second statistical distribution, and determining an indicator. Also, the method includes processing information associated with the indicator, determining a confidence level, processing information associated with the confidence level, and determining whether the characteristic is stable.

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Shanghai, China

Jinghua Ni