Yangtze Memory Technologies Co., Ltd.

Jing Wei

Yan Wang

Yang Zhang

Teng Chen

Kuriyama Masao

Xiaojiang Guo

Masao Kuriyama

Zhihong Li

Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bit line and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bit line can include a first bit line segment coupled to the first memory string group and a second bit line segment coupled to the second memory string group. The buffer can be coupled to the memory array by the bit line. The memory array and the buffer can be included in separate first and second dies, respectively, and the first die can be bonded to the second die.

Page buffer circuit with bit line select transistor

A method includes performing a programming operation on the memory cell using incremental step pulse programming. The programming operation includes applying one or more first voltage steps to the word line using a first step value to increase a threshold voltage of the memory cell toward a programming state. The programming operation also includes determining a quantity of memory cells that have a threshold voltage between first and second verification voltages. The second verification voltage is less than the first verification voltage and outside of a range of threshold voltages corresponding to the programming state. The programming operation also includes determining a step adjustment value based on the determining of the quantity. The programming operation also includes adjusting the first step value using the step adjustment value.

Memory device, programming method of memory device, and memory system

The present disclosure provides a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes; a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane. The plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits.

Memory device, the operation method thereof and memory system

Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path.

Growing community of inventors

Wuhan, China

Jing Wei