Intel Corporation

Micron Technology Incorporated

Other

Jing Ling

Juan-Carlos Calderon

Jean-Michel Caia

Soowan Suh

Vivek Joshi

Anguo Tony Huang

Wei P Chen

Rajat Agarwal

Steve John Clohset

Sreenivas Mandava

Daniel W Liu

Alejandro Lenero Beracoechea

Vasan Karighattam

Rodrigo Gonzalez

Kuljit Singh Bains

Mahesh S Natu

Wei Wu

Theodros Yigzaw

Deep K Buch

John G Holm

Debaleena Das

Mark T Feuerstraeter

James Earl McCormick, Jr

Andrew M Rudoff

Kjersten E Criss

Eduard Lecha

Edward J Pullin

Hsing-Min Chen

Meera Ganesan

George H Huang

Reza E Daftari

Vaibhav Singh

Augusto Alcantara

Wei Chen

Anguo Huang

A memory controller including memory address decode circuitry that detects silent data errors that occur in the memory address decode circuitry during runtime is provided. The memory address decode circuitry includes address decode circuitry to covert a received physical address to a memory address, reverse address decode circuitry to convert the memory address to a second physical address and address compare circuitry to compare the received physical address and the second physical address to detect a silent error.

Detection of data corruption in memory address decode circuitry

A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow without needing to send another read to the memory for the data. The read data is stored in a read data buffer (RDB) at the memory controller when the read data is received from memory. The memory controller has an error detection path from the RDB to the host and an error correction path. Read data that has no errors can be sent directly to the host. Instead of flushing the RDB in response to the error detection, the memory controller executes a retry flow, where the RDB provides the read data to the error correction path for error correction.

Fast memory ECC error correction

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory

An embodiment of a memory apparatus may include a system memory, and a memory manager communicatively coupled to the system memory to determine a first amount of system memory needed for a boot process, initialize the first amount of system memory, start the boot process, and initialize additional system memory in parallel with the boot process. Other embodiments are disclosed and claimed.

Boot process with parallel memory initialization

Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Dynamically changing lockstep configuration

In one embodiment, a method includes receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

Differential delay compensation

In one embodiment, a method includes recording, for each of a plurality of data frames, a virtual write address including a multiframe indicator and a byte number indicator; and reading a group of associated data frames identified by corresponding multiframe indicators and byte number indicators. The reading is based on determining a minimum write address from a plurality of physical write addresses in the group of associated data frames by comparing virtual write addresses of all members in the group.

In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises interleaving data in a predetermined format and controlling distribution of the data irrespective of the format received such that the data can be processed at the destination and passed to downstream components.

Method and apparatus enabling concurrent processing of contiguously and virtually concatenated payloads

A method and apparatus for determining a loss of alignment defect in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise performing specific evaluations and assessments of conditions under normal conditions as well as evaluations and assessments under LCAS conditions where additional members may be added using the LCAS ADD state.

Method and apparatus for detecting and managing loss of alignment in a virtually concatenated group

A method and apparatus for transferring data traffic, such as in a SONET/SDH environment, is provided. Two designs are presented, each utilizing a dual device design, where one device performs GFP Framing and the other device performs GFP-T adaptation. The method and apparatus include a first device having a first device FIFO, the first device configured to receive data and assemble data into packets and transfer data across a packet interface when the first device FIFO contains more than N bytes. A second device comprises a second device FIFO, the second device configured to receive data packets from the packet interface and utilize a plurality of thresholds to maintain a quantity of data in the second device FIFO within a predetermined range. Depending on the design employed, control codes, such as 65B_PAD control codes, may be added in the first device under certain conditions to facilitate data transfer.

Transporting stream client signals via packet interface using GFP mapping

In a communication system that uses virtually concatenated payloads, techniques to determine when to declare and when to clear alarm indication signal (AIS) for a group. The declaration of AIS for a group may occur based on when declaration of AIS for a member of a group occurs. The clearing of group AIS may occur based on when clearing of AIS by a last member of a group to clear AIS occurs.

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Fremont, CA, United States of America

Jing Ling