International Business Machines Corporation

Wisconsin Alumni Research Foundation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Trafficcast International, Inc.

Globalfoundreis Inc.

Jing Li

Chung H Lam

Robert K Montoye

Bing Dai

Kailash Gopalakrishnan

Alejandro Gabriel Schrott

Matthew Joseph BrightSky

Norma Edith Sosa Cortes

Dennis Merton Newns

Edward William Kiewra

Glenn John Martyna

Binquan Luan

Jialiang Zhang

Soroosh Khoram

David Lok

Rathna Gundloori

Dinesh C Verma

Leland Chang

John Kenneth DeBrosse

Scott C Lewis

Weiyuan John Kao

Yue Zha

Weiyun John Kao

A computer architecture for graph processing employs a high-bandwidth memory closely coupled to independent processing elements for searching through a graph using a first set of processing elements operating simultaneously to determine neighbors to a current frontier and second processing elements operating simultaneously to determine a next frontier, this process being repeated to search through graph nodes.

High-speed graph processor for graph searching and simultaneous frontier determination

A spatially programmed logic circuit (SPLC) array system performs spatial compilation of programs for use in the SPLCs to produce standardized compiled blocks representing predetermined portions of an SPLC. The blocks may be freely relocated in an SPLC after compilation by editing of the compiled file. Inter-block communication circuitry allows joining of blocks within an SPLC or across SPLCs to allow scalability and accommodation of different programs with efficient utilization of an SPLC for multiple programs, again without recompilation.

Spatially programmed logic array architecture

A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.

Computer architecture for high-speed, graph-traversal

An associative processor separates the arithmetic operation of addition from the carry process to pre-compute contingent carries before the addition which then allows improved parallelism in the addition process. A portion of the contingent carry computation may also be conducted in parallel. The result is higher-speed operations resulting from increased parallelism.

Associative computer providing semi-parallel architecture

An associative memory that can be integrated with standard computer memory flexibly reduces its parallelism to match the memory bus speed thereby providing substantial increases in memory density possible by a multiplexing of sense amplifiers that otherwise dominate the memory structure. Apparent parallel operation is provided by an accumulator that reassembles the multiplex data. Higher memory density makes dual use of the associative memory as a content addressable memory and random-access memory possible.

High density content addressable memory

A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory elements to be used as local memories (including content addressable memories or random access memories), logic elements or interconnect elements. The ability to dynamically change the function of any of these tiles allows tight integration of memory and logic tailored to particular calculation problems reducing costs in data transfer.

Computer architecture using compute/storage tiles

A computer memory provides for range-matching capabilities using a hybrid combination of transistors and multiple resistive memory devices serving in a dual capacity as storage and logic. The result is an extremely compact, nonvolatile range-matching, content addressable memory.

Nonvolatile range-checking content addressable memory

A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

Memory controller for memory with mixed cell array and method of controlling the memory

A dynamic self-adjusting memory storage device and method of operating. The device includes a plurality of adjustable-size phase change memory (PCM) storage sub-modules connected to and communicating over a bus with a control device. One of the plurality of adjustable-size memory storage sub-modules is in a stand-by mode of operation. The control device implements steps to: determine, based on a switching criteria, when the memory storage device needs to be switched to a different operation mode; select one or more adjustable-sized memory storage sub-modules for switching to said different operation mode; copy stored data from a selected actively operating adjustable-size memory storage sub-module to said adjustable-size memory storage sub-module in said stand-by mode; and change the capacity of the selected actively operating adjustable-size memory storage sub-module after the copying. The dynamic self-adjusting memory capacity method is performed without powering down the memory storage device or paying any timing penalty.

Self-adjusting phase change memory storage module

A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

Electrical coupling of memory cell access devices to a word line

A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.

Memory with mixed cell array and system including the memory

An RC-based sensing method and computer program product to effectively sense the cell resistance of a programmed Phase Change Material (PCM) memory cell. The sensing method ensures the same physical configuration of each cell (after programming): same amorphous volume, same trap density/distribution, etc. The sensing method is based on a metric: the RC based sense amplifier implements two trigger points. The measured time interval between these two points is used as the metric to determine whether the programmed cell state, e.g., resistance, is programmed into desired value. The RC-based sensing method is embedded into an iterative PCM cell programming technique to ensure a tight distribution of resistance at each level after programming; and ensure the probability of level aliasing is very small, leading to less problematic drift.

Drift mitigation for multi-bits phase change memory

A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

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Ossining, NY, United States of America

Jing Li