Yangtze Memory Technologies Co., Ltd.

Wuhan United Imaging Healthcare Co., Ltd.

Jing Gao

Bo Xu

Ping Yan

Chuan Yang

Lei Ding

Lan Fang Yu

Sen Zhang

Zongliang Huo

Lu Zhang

Yang Huang

Chao Xia

Chao Tang

Jie Tan

Mingwu Gan

Guodong Xie

Yinglong Wang

Qiang Shen

Wenbin Zhou

Yang Zhou

ZongLiang Huo

Zhaosong Li

Jing Liu

Feng Lu

Chuanhai Shan

Zhouyang Lu

Zhiyong Lu

Kai Yu

Sheng Peng

Wenbo Zhang

Xiaoming Mao

A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. A first channel structure extends from the semiconductor layer and through a first array region of the first stack. A second stack of alternating second word line layers and second insulating layers are over the first stack. A second channel structure extends from the first channel structure and through a second array region of the second stack. A thickness of a particular first insulating layer, which is positioned closest to the second stack relative to other first insulating layers, is a sum of at least two times an average thickness of the other first insulating layers and at least one time an average thickness of the first word line layers in the first array region.

Three-dimensional NAND memory device and method of forming the same

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a conductor/insulator stack over a substrate, forming a dielectric layer of a dielectric material including atomic hydrogen over a part of the conductor/insulator stack, and performing a thermal process to release the atomic hydrogen from the dielectric material and diffuse the atomic hydrogen into the conductor/insulator stack.

Three-dimensional memory device and fabrication method

Three-dimensional (3D) NAND memory devices and methods are provided. A fabrication method includes forming a semiconductor layer over a substrate, forming an opening that extends partially through the semiconductor layer, depositing a first stack layer and a second stack layer that are alternately stacked over a sidewall of the opening and over the semiconductor layer, and filling the opening with a dielectric material to form an alignment mark.

Three dimensional (3D) memory device and fabrication method

The present disclosure is related to systems and methods for orthosis design. The method includes obtaining a three-dimensional (3D) model associated with a subject. The method includes obtaining one or more reference images associated with the subject. The method includes determining, based on the 3D model and the one or more reference images, orthosis design data for the subject. The orthosis design data may be used to determine an orthosis for the subject.

Systems and methods for orthosis design

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.

Three-dimensional memory device with corrosion-resistant composite spacer

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Three-dimensional memory devices and fabricating methods thereof

A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

A method for forming a three-dimensional (3D) memory device is disclosed. In some embodiments, the method includes forming an alternating dielectric stack on a substrate, and forming a plurality of channel holes penetrating the alternating dielectric stack vertically to expose at least a portion of the substrate. A first mask can be formed to cover the channel holes in a first area and expose the channel holes in a second area. The method also includes forming a recess in the alternating dielectric stack in the second area, followed by forming a second mask in the recess. The second mask covers the channel holes in the second area and exposes the channel holes in the first area. The memory film at bottom of each channel hole in the first area can therefore be removed, while the memory film in the second area can be protected by the second mask.

Dual deck three-dimensional NAND memory with channel dips and method for forming the same

Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of conductor/dielectric layer pairs, a plurality of memory strings each extending vertically through the memory stack, a slit contact disposed laterally between the plurality of memory strings, and a composite spacer disposed laterally between the slit contact and at least one of the memory strings. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film disposed laterally between the first silicon oxide film and the second silicon oxide film.

Growing community of inventors

Hubei, China

Jing Gao