Shanghai Huali Integrated Circuit Corporation

Shanghai Huali Microelectronics Corporation

Jinde Gao

Qiang Chen

Cheng Wu

Yanrong Qiu

Shuqing Duan

A method of failure analysis for locating open circuit defect in a metal layers, comprising: providing a chip sample having a metal layer, with an open circuit defect; delaminating the chip to expose the metal layer; depositing a metal conductive layer on the metal layer; removing a portion of the metal conductive layer to expose the metal layer; depositing a non-conductive protective layer to cover the exposed metal layer and any remaining portions of the metal conductive layer; preparing a TEM slice sample which comprises the metal layer, the remaining portions of the metal conductive layer, and the non-conductive protective layer; performing a VC analysis on the TEM slice sample to determine the defect position of the open circuit defect; and analyzing the defect position of the open circuit defect.

Method of failure analysis for defect locations

The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step: forming a coating mark at the first scratch mark on the sample; step: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.

Method for locating open circuit failure point of test structure

The present application discloses a method for preparing a TEM sample, including the following steps: step 1: providing a thin-film pre-sample with undesirable voids; step 2: performing a first cutting with a first FIB to form the TEM sample located in the target region of the thin-film pre-sample. The first thickness is reached after the first cutting. The voids are exposed from the front surface or the back surface of the TEM sample after the first cutting; step 3: depositing a first material layer by an ALD process to fill the voids in the TEM sample; step 4: performing the second cutting with a second FIB to form the target thickness of the TEM sample in the target region of the thin-film pre-sample. The present application can reduce or eliminate ion beam cutting marks related to the voids in the thin-film pre-sample.

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Shanghai, China

Jinde Gao