Samsung Electronics Co., Ltd.

Jin-Yub Lee

Dae-Sik Park

Jin-wook Lee

Sang-Won Hwang

Ho-kil Lee

Chul-Ho Lee

Dong-Kyu Youn

Min-gun Park

Seung-Jae Lee

Young-Joon Choi

Jong-Hoon Lee

Sang-chul Kang

Yong-Taek Jeong

Jin-Kook Kim

Sang-Chul Kang

Seok-Heon Lee

You-Sang Lee

Jin-kook Kim

Yohan Lee

June Hyung Lee

Yoon-Hee Choi

Tae-Gyun Kim

Chan-Ik Park

Bum-Soo Kim

Won-Tae Kim

Bo-Geun Kim

Sung-Joon Kim

Su-Chang Jeon

Seong-Kue Jo

June-Hong Park

Jae-Woo Im

Jung-Ho Song

Venkataramana Gangasani

Hyung-Min Kim

Sung-Kyu Jo

Sungwhan Seo

Min-Gun Park

Kwang-Yoon Lee

Joon Young Kwak

Hoo-Sung Kim

Dojeon Lee

Hyung-Seok Kang

Ho-Kil Lee

Eun-suk Kang

Sang-So Park

Seok-Heon Samsung Electronics Taiwan Co Ltd Lee

A nonvolatile memory device includes a voltage generating circuit configured to generate voltages applied to word lines corresponding to a selected memory block among memory blocks. The voltage generating circuit includes voltage source lines having linear voltages, a first voltage generating unit configured to generate a first voltage and apply the generated first voltage to a first voltage source line among the voltage source lines, a second voltage generating unit configured to generate a second voltage and apply the generated second voltage to a second voltage source line among the voltage source lines, and a linear voltage generator having a resistor string connected between the first voltage source line and the second voltage source line. At least one of the voltage source lines has a voltage distributed between the first voltage and the second voltage.

Nonvolatile memory device, storage device having the same, operating method thereof

A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.

Non-volatile memory device and method of operating

A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied.

Voltage supply controller, nonvolatile memory device and memory system

A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.

Nonvolatile memory device and method of reading data in nonvolatile memory device

A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.

Flash memory device and flash memory system including buffer memory

A semiconductor memory device includes a memory core and a fail detection circuit. The memory core includes a memory cell array having a plurality of memory cells. The fail detection circuit compares read data with test data to generate a comparison signal representing whether each of the memory cells is failed or not, and accumulates and stores fail information of the memory cells corresponding to a plurality of addresses to output accumulated fail information. The read data are read out from the memory cells in which the test data are written.

Semiconductor memory device and system including the same

A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may include a register for storing first and second flag signals each indicative of selections of corresponding memory chips, a comparator circuit for comparing the first and second flag signals in the register with a reference signal to generate a flash access signal and a buffer access signal, and a controller for controlling the buffer memory and the flash memory in response to the flash access signal and the buffer access signal.

Dual memory chip package operable to access heterogeneous memory chips

A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

Reference voltage generating circuit

According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external input address may be decoded into a block address and a page address. The block size of the flash memory device may be changed from the first block size to the second block size by shifting at least one bit of the block address to the page address or shifting at least one bit of the page address to the block address.

Flash memory device and method of changing block size in the same using address shifting

In a read method for a memory device, a bit line is set with data in a first memory cell; and the data on the bit line is stored in a register. The data in the register is transferred to a data bus while setting the bit line with data in a second memory cell. In another read method for a memory device, a bit line of a first memory cell is initialized and the bit line is pre-charged with a pre-charge voltage. Data in a memory cell on the bit line is developed, and a register corresponding to the bit line is initialized. The data on the bit line is stored in the register. The data in the register is output externally while performing the initializing, pre-charging, making and initializing to set the bit line with data in a second memory cell.

Method and device for performing cache reading

A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

Method of verifying programming operation of flash memory device

Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

Multi-bit flash memory devices having a single latch structure and related programming methods, systems and memory cards

A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode.

Semiconductor device with reduced standby failures

A flash memory device includes a cell array and a voltage supplying and selecting portion. The cell array includes multiple word lines, and the voltage supplying and selecting portion is configured to generate at least two different voltages to be supplied to the word lines of the cell array during an erase operation.

Flash memory device and method of erasing flash memory device

Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.

Multi-block memory device erasing methods and related memory devices

Growing community of inventors

Seoul, South Korea

Jin-Yub Lee