Skhynix Inc.

Amkor Technology, Inc.

Jin Woo Park

Bae Yong Kim

Dong In Kim

Dong Hee Lee

Yeon Seung Jung

Kwang Sun Oh

Jong Hoon Kim

Bok Kyu Choi

Jae Hoon Lee

Sung Su Park

Juil Eom

Joo Wan Hong

Sang Gyu Lee

A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first through mold via (TMV) for connection spaced apart from a first semiconductor chip in an X-axis direction, a first TMV for bypass spaced apart from the first semiconductor chip in a Y-axis direction, and a first redistribution line (RDL) pattern connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second TMV for connection spaced apart from a second semiconductor chip in the Y-axis direction and another RDL pattern connecting the second semiconductor chip to the second TMV for connection. the second sub-package is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.

Stack packages including through mold via structures

A semiconductor package and a method of manufacturing the semiconductor package may be provided. The semiconductor package may include a first semiconductor chip disposed on a first surface of an interconnection layer, a second and a third semiconductor chips disposed on a second surface of the interconnection layer. The semiconductor package may include a thermal transfer plate disposed between the second and third semiconductor chips, contacting the second surface of the interconnection layer, and overlapping with the first semiconductor chip. The thermal transfer plate may be configured to provide a heat radiation path.

Semiconductor packages relating to thermal transfer plate and methods of manufacturing the same

A semiconductor package and or method of fabricating a semiconductor package may be provided. The semiconductor package may include a package substrate. The semiconductor package may include a first semiconductor die coupled to the package substrate by first interconnectors. The semiconductor package may include a second semiconductor die coupled to the first semiconductor die by second interconnectors. The second semiconductor die may be coupled to the substrate.

Semiconductor packages including interconnectors and methods of fabricating the same

A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.

Semiconductor devices having through electrodes, methods of fabricating the same, electronic systems including the same, and memory cards including same

A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.

Semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same, and electronic systems including the same

A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar.

Growing community of inventors

Icheon-si, South Korea

Jin Woo Park