Magnachip Semiconductor, Inc.

Coupang, Corporation

Jin Won Jeong

Jae Sik Choi

Byeung Soo Song

Jong Won Lee

Ji Won Hwang

Seon Sook Hong

Do Young Kim

Sang Min Jeon

Hye Ji Lee

Da Young Kim

Sang Min Jun

Woo Jung Park

Kyeong Suk Jin

Jang Hee Lee

Young Hun Jun

Jong Woon Lee

Dong Ki Shim

Jin Han Bae

Young Sug Seong

Dong Keun Lee

A semiconductor die forming method includes preparing a wafer, forming a low-k dielectric layer on the wafer, forming a metal pad on the low-k dielectric layer, forming a passivation layer on the metal pad, patterning the passivation layer, laser grooving the low-k dielectric layer using an ultrashort pulse laser, and cutting the wafer by mechanical sawing to form one or more semiconductor dies.

Semiconductor die forming and packaging method using ultrashort pulse laser micromachining

A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.

Fabrication method of semiconductor die and chip-on-plastic packaging of semiconductor die

A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

Method for forming semiconductor die with die region and seal-ring region

The present disclosure provides systems and methods for monitoring inventory transfer in real-time, comprising a memory storing instructions and a processor configured to execute the instructions to receive a tote identifier associated with a tote configured to store one or more products and receive a container identifier associated with a container configured to store the tote. The processor is configured to receive, from a user device in the first fulfillment center, a code associated with a vehicle for transferring the container from a first to a second fulfillment center, receive, from a user device in the second fulfillment center, the code associated with the vehicle, receive, from the user device in the second fulfillment center, at least one of the container identifier or the tote identifier, and validate the transfer of the first product, based on the code and at least one of the container identifier or the tote identifier.

Systems and methods for electronic monitoring of inventory transfer

Provided is a method of recognizing an item as a removal target based on expiration date-related information of the item, acquiring information regarding an actual quantity of the removal target and a remaining quantity among the actual quantity, and updating information regarding stock based on the acquired information, and an electronic apparatus therefor.

Electronic apparatus and operation method thereof

A semiconductor package includes a first metal interconnection disposed in a semiconductor chip, a first bump group configured to be connected to the first metal interconnection, a first inner lead pattern group configured to be connected to the first bump group, a second metal interconnection disposed in the semiconductor chip, a second bump group configured to be connected to the second metal interconnection; and a second inner lead pattern group configured to be connected to the second bump group, wherein a density of the first metal interconnection is greater than a density of the second metal interconnection, such that a first pitch of the first lead pattern group is greater than a second pitch of the second lead pattern group.

Semiconductor package with inner lead pattern group and method for manufacturing the semiconductor package

A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.

Method of forming and packaging semiconductor die

A semiconductor package manufacturing method includes preparing a flexible film including input wire patterns and output wire patterns, preparing a semiconductor chip including metal bumps, attaching the semiconductor chip to one side of the flexible film, such that the metal bumps are connected to either one or both of the input wire patterns and the output wire patterns, and attaching a first absorbing and shielding tape to another side of the flexible film, wherein the first absorbing and shielding tape includes an absorption film and a protective insulating film disposed on the absorption film.

Semiconductor package and method of manufacturing semiconductor package

A test socket of a flexible semiconductor chip package includes a first bending jig having a convex contour, a second bending jig having a concave contour, and a semiconductor chip package. The second bending jig is disposed to matingly engage the first bending jig. The semiconductor chip package is disposed between the first bending jig and the second bending jig, and includes a flexible tape and a semiconductor chip. The semiconductor chip is disposed on a surface of the flexible tape. Each of the first and second bending jigs has a horizontal length longer than a length of the semiconductor chip and less than a length of the flexible tape.

Growing community of inventors

Seoul, South Korea

Jin Won Jeong