Samsung Electro-Mechanics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Samsung Electronics Co., Ltd.

Iucf-Hyu

Jin Seon Park

Myung Mo Sung

Jinwon Jung

Hongbum Kim

Young Sik Hur

Doo Hwan Lee

Jung Soo Byun

Sang Chul Lee

Seungho Lee

Yong Ho Baek

Jung Won Lee

Jung Chul Gong

Won Wook So

Yong Duk Lee

Seong Jong Cheon

Sung Yi

Sungjoo Kim

Ho Kyung Kang

Dongkyu Park

Wonkyu Park

Jongbae Kim

Sungha Son

Hak Gu Kim

Mingyu Yoon

Wooyoung Cheon

Kihun Kim

Jinyoung Shin

Seongsoo Kim

Doosoon Park

Wonhong Choi

Hongro Yun

An antenna module includes an antenna substrate including an antenna pattern; a semiconductor package disposed on a lower surface of the antenna substrate, electrically connected to the antenna substrate, and having a semiconductor chip embedded therein; and an electronic component disposed at a side of the antenna substrate, electrically connected to the antenna substrate, and spaced apart from the semiconductor package by a predetermined distance. The antenna module includes a connection substrate connected to a portion of the antenna substrate, the connection substrate having an extension portion extending outward from the side of the antenna substrate, and the electronic component is disposed on the extension portion of the connection substrate to electrically connect to an inner wiring layer of the antenna substrate.

Antenna module

A layer forming method according to one embodiment of the present invention contains a source gas dosing/pressurizing step of dosing a source gas into a chamber having a substrate loaded therein in a state in which the outlet of the chamber is closed, thereby increasing the pressure in the chamber and adsorbing the source gas onto the substrate; a first main purging step of purging the chamber, after the source gas dosing/pressurizing step; a reactive gas dosing step of dosing a reactive gas into the chamber, after the first main purging step; and a second main purging step of purging the chamber, after the reactive gas dosing step.

Method and apparatus for forming layer, metal oxide transistor and fabrication method thereof

A display apparatus is provided. The display apparatus includes a display; a main body on which the display is mounted; a cover; a mounting member configured to separably mount the main body to the mounting member; and a guide member disposed at a back surface of the main body, the guide member including a plate member and side-surface members extending from opposite side surfaces of the plate member, wherein each of the side-surface members has an inclined shape.

Display apparatus

A chip radio frequency package includes a substrate including a first cavity, first and second connection members, a core member, a radio frequency integrated circuit (RFIC) disposed on an upper surface of the substrate, and a first front-end integrated circuit (FEIC) disposed in the first cavity. The core member includes a core insulating layer and a core via that penetrates the core insulating layer. The first connection member has a structure in which a first insulating layer and a first wiring layer are stacked. The second connection member has a second structure in which a second insulating layer and a second wiring layer are stacked. The RFIC inputs or outputs a base signal and a first radio frequency (RF) signal having a frequency higher than a frequency of the base signal, and the first FEIC inputs or outputs the first RF signal and a second RF signal.

Chip radio frequency package and radio frequency module

Provided are P-type semiconductor layer, P-type multilevel element, and manufacturing method for the element. The P-type multilevel element comprises a gate electrode, an active structure overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the active structure, and source and drain electrodes electrically connected to both ends of the active structure, respectively. The active structure has a first P-type active layer, a second P-type active layer, and a barrier layer disposed between the first P-type active layer and the second P-type active layer. A threshold voltage for forming a channel in the first P-type active layer and a threshold voltage for forming a channel in the second P-type active layer have different values.

P-type semiconductor layer, P-type multilevel element, and manufacturing method for the element

A layer forming method according to one embodiment of the present invention comprises: a source gas dosing/pressurizing step of dosing a source gas into a chamber having a substrate loaded therein in a state in which the outlet of the chamber is closed, thereby increasing the pressure in the chamber and adsorbing the source gas onto the substrate; a first main purging step of purging the chamber, after the source gas dosing/pressurizing step; a reactive gas dosing step of dosing a reactive gas into the chamber, after the first main purging step; and a second main purging step of purging the chamber, after the reactive gas dosing step.

A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band,

Layer, multilevel element, method for fabricating multilevel element, and method for driving multilevel element

A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.

Embodiments of the invention provide a method of manufacturing an embedded printed circuit board, which includes the following operations in the order presented: a first operation of forming a first cavity and a third cavity, disposing a first device in the first cavity and disposing a third device in the third cavity; a second operation of forming a second cavity and a fourth cavity, disposing a second device in the second cavity; a third operation of providing an insulating member; a fourth operation of disposing a first base substrate and a second base substrate and pressure laminating the first base substrate, the second base substrate, and the insulating member together; and a fifth operation of forming a first copper clad laminate and forming a second copper clad laminate.

Embedded printed circuit board and method of manufacturing the same

Disclosed herein is a printed circuit board, including: a substrate including an insulation layer in which a cavity is formed; an electronic component mounted in the cavity of the substrate and having connection terminals; an insulation material layer formed on one side of the substrate to bury the electronic component; a first circuit layer formed on the other side of the substrate and including a connection pattern connecting with the connection terminals of the electronic component; and a second circuit layer formed on the insulation material layer. The printed circuit board is advantageous in that it can prevent the warpage thereof and ensure the reliability of electrical connection between an electronic component and a circuit layer by adjusting the thickness, thermal expansion coefficient and elastic modulus of insulation layer or the insulating material.

Electronic component-embedded printed circuit board and method of manufacturing the same

Disclosed herein is an electronic component-embedded printed circuit board including: a base plate including an insulating resin layer and circuit layers; and an electronic component embedded in the insulating resin layer, wherein the insulating resin layer has a thickness 1.3&#x2dc;3 times greater than that of the electronic component. The electronic component-embedded printed circuit board has an optimum thickness ratio of its constituents in order to minimize the warpage thereof at the time of manufacturing the same.

Electronic component-embedded printed circuit board

Disclosed is an embedded printed circuit board, in which electronic devices having different thicknesses can be embedded together, thus achieving highly dense electronic devices, and when electronic devices having considerably different thicknesses are embedded, two electronic devices which are comparatively thinner can be embedded in a perpendicular direction, thus reducing an embedding area and suppressing warping of the printed circuit board, and an insulating member the thickness of which is variably adjusted is interposed between base substrates, so that spaces between the electronic devices are completely filled therewith, thus solving the problem of void defects, resulting in reliable printed circuit boards, and, when a base substrate includes a core made of metal, the printed circuit board can less warp. Also a method of manufacturing the embedded printed circuit board is provided.

Growing community of inventors

Seoul, South Korea

Jin Seon Park