Samsung Electronics Co., Ltd.

Jin-seo Noh

Yoon-Ho Khang

Dong-seok Suh

Sang-mock Lee

Sung-ho Park

Joong S Jeon

Mi-jeong Song

Eun-ju Bae

Vassili Leniachine

Youn-seon Kang

Jin-heong Yim

Tae-wan Kim

Eun-sik Kim

Tae-sang Park

Woong-chul Shin

Ki-joon Kim

Yoon-ho Khang

Joong-S Jeon

Hong-seog Kim

Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal gate is formed of a metal nitride that contains Al or Si and includes upper and lower portions where the content of Al or Si is relatively high and a central portion where the content of Al or Si is relatively low.

Semiconductor device having a metal gate with a low sheet resistance and method of fabricating metal gate of the same

Provided are a phase change layer and a method of forming the phase change layer and a phase change memory device including the phase change layer, and methods of manufacturing and operating the phase change memory device. The phase change layer may be formed of a quaternary compound including an amount of indium (In) ranging from about 15 at. % to about 20 at. %. The phase change layer may be InGeSbTe, wherein an amount of germanium (Ge) ranges from about 10 at. %&#x2266;b&#x2266;about 15 at. %, an amount of antimony (Sb) ranges from about 20 at. %&#x2266;c&#x2266;about 25 at. %, and an amount of tellurium (Te) ranges from about 40 at. %&#x2266;d&#x2266;about 55 at. %.

Phase change layer and method of manufacturing the same and phase change memory device comprising phase change layer and methods of manufacturing and operating phase change memory device

Insulating impurities may be uniformly distributed over an entire or partial region of the phase change material. The PRAM may include a phase change layer including the phase change material. The insulating impurity content of the phase change material may be 0.1 to 10% (inclusive) the volume of the phase change material. The insulating impurity content of the phase change material may be adjusted by controlling the power applied to a target including the insulating impurities.

Phase change material for use in a phase change random access memory, the phase change material having uniformly distributed insulating impurities

Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate;

Method of fabricating Schottky barrier transistor

In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film.

Phase change memory devices and fabrication methods thereof

A PRAM and a fabricating method thereof are provided. The PRAM includes a transistor and a data storage capability. The data storage capability is connected to the transistor. The data storage includes a top electrode, a bottom electrode, and a porous PCM layer. The porous PCM layer is interposed between the top electrode and the bottom electrode.

Phase-change ram and method for fabricating the same

Provided is a method of operating a phase change random access memory comprising a switching device and a storage node comprising a phase change layer. The method includes applying a reset current passing through the phase change layer from a lower portion of the phase change layer toward an upper portion of the phase change layer and being smaller than 1.6 mA to the storage node to change a portion of the phase change layer into an amorphous state. The set voltage is in an opposite direction is exemplary embodiments, and a connector is of small cross-sectional area.

Method of operating and structure of phase change random access memory (PRAM)

Provided is a semiconductor device and a method of fabricating a metal gate in the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, the metal gate is formed of a mixture of a metal nitride and a metal carbide, and a work function of the metal gate is determined according to ratios of the metal nitride with respect to the metal carbide.

Semiconductor device and method of fabricating metal gate of the same

Phase change layer including indium and method of manufacturing the same and phase change memory device comprising phase change layer including indium and methods of manufacturing and operating the same

A phase change random access memory (PRAM), and a method of operating the PRAM are provided. In the PRAM comprising a switching element and a storage node connected to the switching element, the storage node comprises a first electrode, a second electrode, a phase change layer between the first electrode and a second electrode, and a heat efficiency improving element formed between the first electrode and the phase change layer. The heat efficiency improving element may be one of a carbon nanotube (CNT) layer, a nanoparticle layer, and a nanodot layer, and the nanoparticle layer may be a fullerene layer.

Phase change random access memory and method of operating the same

A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric film covering the bottom electrode, and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film, forming a bottom electrode contact plug by filling the bottom electrode contact hole with a plug material, forming a fullerene layer on a region including at least an upper surface of the bottom electrode contact plug and sequentially stacking a phase change layer and an upper electrode on the fullerene layer. The method may further include forming a switching device on a substrate and a bottom electrode connected to the switching device, forming an interlayer dielectric film covering the bottom electrode and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film.

Method of fabricating phase change RAM including a fullerene layer

A phase change memory device includes a switch and a storage node connected to the switch. The storage node includes a first electrode, a phase change layer and a second electrode. The phase change layer is formed of an InSbTe compound doped with Ge. In a method of operating a phase change memory including a switch and a storage node, the switch is maintained in an on state, and a first current is applied to the storage node.

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Seoul, South Korea

Jin-seo Noh