Sandisk Technologies Inc.

Facebook, Inc.

Jin Liu

Johann Alsmeier

Yanli Zhang

Murshed Chowdhury

Raghuveer S Makala

James K Kai

Hiroyuki Ogawa

Yao-Sheng Lee

Jixin Yu

Chun Ge

Yoko Furihata

Tong Zhang

Hiroyuki Kinoshita

Senaka Kanakamedala

Tadashi Nakamura

Matthias Baenninger

Marika Gunji-Yoneoka

Kazuya Tokunaga

Jiyin Xu

Yoshihiro Kanno

Deepanshu Dutta

Xiang Yang

Jayavel Pachamuthu

Huai-Yuan Tseng

Dengtao Zhao

Fumiaki Toyama

Masatoshi Nishikawa

Andrew C Lin

Zhongguang Xu

Yuki Mizutani

Kazutaka Yoshizawa

Gregory Paul Whalin

Dai Iwata

Yasuaki Yonemochi

Erica Jean Virtue

Camilla Huang

An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same

Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.

Programming selection devices in non-volatile memory strings

A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

Three-dimensional memory device with thickened word lines in terrace region and method of making thereof

In one embodiment, a method includes receiving a text post from a client system of a first user of an online social network and parsing the text post to identify a query associated with the post. The method includes receiving one or more comments responsive to the text post from one or more second users of the online social network and determining, for each of the comments, whether the comment includes a recommendation responsive to the query. Moreover, the method includes identifying, for each comment with a responsive recommendation, one or more objects of the online social network associated with the recommendation and generating an aggregated recommendation list responsive to the query, where the list includes references to one or more of the identified objects.

Recommendations from comments on online social networks

Three-dimensional memory device with thickened word lines in terrace region

Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.

Three dimensional NAND memory device with common bit line for multiple NAND strings in each memory block

A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

Methods and apparatus for three-dimensional NAND non-volatile memory devices with side source line and mechanical support

A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

Through-memory-level via structures for a three-dimensional memory device

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. An isolation trench laterally extends along a horizontal direction and divides at least two topmost electrically conductive layers. Two conductive rail structures are located on lengthwise sidewalls of the isolation trench and are electrically shorted to respective segments of the at least two topmost electrically conductive layers.

Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.

Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

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Milpitas, CA, United States of America

Jin Liu