Other

Macronix International Co., Ltd.

Advanced Micro Devices Corporation

Jin-Lien Lin

Takao Akaogi

Lee Edward Cleveland

Ali K Al-Shamma

Kendra Nguyen

Boon Tang Teh

Yong K Kim

I-Long Lee

Yong Bae Kim

A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.

Memory line discharge before sensing

A voltage boost circuit ( ) for a flash memory ( ) includes a boosting circuit ( ), which is capable of boosting a portion of a power supply voltage (V ) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array ( ) of the memory. The voltage boost circuit further includes a balancing or clamping circuit ( ) for providing a nonzero adjustment voltage (V ) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

Voltage boost level clamping circuit for a flash memory

A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.

Word line decoding architecture in a flash memory

A voltage boost circuit (,) for a memory (,) includes a boosting circuit (,) which is coupled to a boosted node (,) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (,) coupled to the boosted node and including a switchable zero-threshold transistor (,) for resetting the boosted node to a reset voltage (VCC).

Voltage boost reset circuit for a flash memory

A voltage detector circuit of a nonvolatile memory integrated circuit for determining the voltage potential of a supply voltage is provided. The voltage detector includes a first MOS device, a second MOS device, a bias circuit for adjusting the current through the first and second MOS devices that is responsive to the level of the supply voltage, and an output circuit that provides an output signal indicating the level of the supply voltage. The bias circuit may comprise a voltage divider circuit which provides a predetermined ratio of the supply voltage to the gate of one or both of the MOS devices. The voltage divider circuit may comprise MOS devices configured as resistive devices in series. The current through the MOS devices is provided to the output circuit, and the output circuit utilizes a measure of the difference in the current levels to determine the level of the voltage supply and provide the appropriate output signal. The output circuit may comprise a current mirror circuit that tries to equate the current flowing through the first and second MOS devices, and a gain stage. The gain stage may comprise a series of CMOS inverters to boost the output signal which in one case is a CMOS high signal when the supply voltage is greater than some predetermined voltage and is a CMOS low signal when the supply voltage is less than some predetermined voltage. In one embodiment the V,and aspect ratios of the first and second MOS devices are equal. However, in other embodiments, the V,and aspect ratios may be changed so as to act in combination with the bias circuit to adjust the currents in response to the level of the voltage supply. The detector may also include a drain voltage controller which acts in combination with the bias circuit to adjust the currents.

Voltage detection circuit

In a floating gate memory that has a buffer that can be coupled to a set of floating gate memory cells in the memory, a method of writing to a selected portion of the set of floating gate cells. For example, a method of writing a byte to a floating gate memory where the memory uses a page buffer reads and writes to an entire row of cells at a time. Store contents of the set of floating gate cells into the buffer, store the data into a portion of the buffer corresponding to the selected portion of the set of floating gate cells, and store contents of the buffer into the set of floating gate cells. An improved floating gate memory is disclosed in which data may be loaded into a portion of the floating gate cells in a set of cells that may be coupled to a buffer.

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Sunnyvale, CA, United States of America

Jin-Lien Lin