Korea Advanced Institute of Science and Technology

Samsung Electronics Co., Ltd.

Jin Hyuck Yu

Je Kook Kim

You So Cheon

Sung-Il Cho

Jung Keun Kim

Jung Joon Yoo

Hyuek Jae Lee

Jong Yeon Kim

Se-gi Byun

Su Hyeon Kim

Min-woo Song

Woong-Sun Lee

Woong Sun Lee

A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

Semiconductor package and method of manufacturing the same

An integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage.

Integrated circuit and cable assembly including the same

The present invention relates to a film-type micro-supercapacitor and a manufacturing method thereof including a method for manufacturing an electrode film by using graphene or graphene oxide, a method for forming a two-dimensional electrode by separating a graphene or graphene oxide electrode film into two independent electrodes through patterning, a method for forming an in-plane structure of the two-dimensional electrode, a method for forming a current collector on an electrode, and a method for manufacturing a supercapacitor with a micrometer thickness by supplying an electrolyte to the two-dimensional electrode.

Film-type supercapacitor and manufacturing method thereof

A voltage biasing circuit includes a metal-oxide-semiconductor (MOS) transistor, a voltage control circuit controlling a voltage between a gate and a source of the MOS transistor to operate the MOS transistor in a sub-threshold range, and a capacitor connected to the MOS transistor. The voltage biasing circuit may further include a voltage buffer connected between the voltage control circuit and the MOS transistor.

Voltage biasing circuit and data processing system having the same

Disclosed herein is a method of bonding solder pads of a flip-chip package. This invention relates to a method of bonding solder pads having different sizes to each other, when a bonding operation is executed between a chip and a PCB, between chips, or between PCBs. On a side having a larger solder pad, a general solder ball is used. Conversely, on a side having a smaller solder pad, a solder ball having a core is used. The core serves to maintain a predetermined interval between the chip and the PCB or between the chips, after the bonding operation has been completed. The solder bonded parts are aligned with each other so as to perform a final bonding operation. In a conventional flip-chip package, solder pads provided on a bonded part must have the same or similar size. According to this invention, even if the size difference between the solder pads is large, bonding is possible, thus ensuring electrical and mechanical reliability.

Method of bonding solder pads of flip-chip package

Disclosed is a fabrication method of a printed circuit board, consisting of plating a metal on a pattern-formed metallic substrate to form a conductive metal line; forming a polymer layer as a base substrate over the conductive metal line-formed metallic substrate and drying the formed polymer layer; forming a via hole in the polymer layer, followed by plugging the formed via hole by electroplating; and removing the metallic substrate. The method is advantageous in terms of maximum efficiency of use of the surface area of PCB, and fineness and high integration of circuits because of not requiring an additional etching process.

Method of manufacturing printed circuit board and multi-layered PCB

Disclosed is a fabrication method of UBM for flip chip interconnections of a semiconductor device, consisting of dipping a patterned wafer into a plating solution containing materials supplying nickel and copper ions, forming a copper layer at a predetermined current density for connection between a chip pad and a solder bump and for residual stress-buffering, and forming a nickel-copper alloy layer at an increased current density for prevention of diffusion between the solder and the pad. The method is advantageous in terms of low fabrication cost due to not requiring an etching process, while meeting the conditions of wettability, diffusion-barrier function and small residual stress required to form UBM on the patterned wafer.

Method of fabricating multilayered UBM for flip chip interconnections by electroplating

A method for making n-type semiconducting diamond by use of CVD in which n-type impurities are doped simultaneously with the deposition of diamond. As the n-type impurities, an Li compound and a B compound, both, are used at once. After doping, a diamond film thus obtained is etched to peel off its surface. The n-type semiconducting diamond is superior in specific resistivity, 10.sup.-2 .OMEGA.cm or less.

Growing community of inventors

Hwaseong-si, South Korea

Jin Hyuck Yu