Apack Technologies Inc.

United Test Center Inc.

Jin-Chyuan Biar

Chong-Ren Maa

Albert Lin

Cheng-Hui Lee

Kuo-Teh Ho

A hole is generated in a substrate. A chip is connected to the substrate by using the chip receiving area of the substrate by using flip chip assembly. The hole is aligned to the chip receiving area of the substrate. Then, a underfill process is performed such that the space between the chip and the substrate will be encapsulated using liquid capsulated material. The liquid capsulated material is injected into the hole from the back side surface of the substrate to the front side surface of the substrate.

Method for improving the reliability of underfill process for a chip

A chip scale packaging method is used to package a single-sided substrate and one or more semiconductor chips. The nonconductive surface of the substrate is provided with one or more chip-implanting adhesive areas by stenciling. The adhesive areas are provided with one or more through holes. The chips are implanted in the adhesive areas of the substrate such that the active surface of each chip is in contact with the adhesive area, and that the bonding pads of the active surface of the chip are corresponding in location to the through holes. Upon completion of the chip implantation, the substrate and the implanted chips are heated under pressure before the bonding pads are connected with the conductive surface of the substrate by a plurality of metal bonding wires. The chips and the through holes are subsequently provided with a passivation layer. Finally, the conductive surface of the substrate is implanted with a plurality of spherical bonding points in a grid array fashion.

Growing community of inventors

Taipei, Taiwan

Jin-Chyuan Biar