Ultratera Corporation

United Test Center Inc.

Jin-Chuan Bai

Chung-Che Tsai

Huan-Ping Su

Soon-Aik Lu

A fabrication method of a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is respectively applied on terminals of the conductive traces. Then, a non-solderable material is applied over the core layer as to cover the conductive traces except for the insulating material, and the non-solderable material is adapted to be surface-flush with the insulating material, allowing the insulating material to be exposed from the non-solderable material. Finally, the insulating material is removed from the core layer to expose the terminals of the conductive traces, wherein the exposed terminals are used as bond pads or bond fingers where solder balls, solder bumps or bonding wires can be bonded. This circuit board is cost-effectively fabricated by simplified processes, and beneficial in precisely exposing bond pads or bond fingers, thereby significantly improving yield of fabricated circuit boards.

Fabrication method of circuit board

A semiconductor device is proposed, in which a chip is placed in an opening penetratingly formed in a substrate in a manner as not to come into contact with the substrate, and an encapsulant formed on the substrate fills up the opening for encapsulating the chip. This arrangement of the chip accommodated in the substrate therefore reduces the overall height of the semiconductor device. Moreover, a plurality of conductive elements disposed on the substrate are also encapsulated by the encapsulant in a manner that, bottom sides of the conductive elements are exposed to outside of the encapsulant, and coplanarly positioned with a bottom side of the encapsulant. This therefore provides good planarity for a bottom side of the semiconductor device, allowing the semiconductor device to be well electrically connected to external devices. A method for fabricating the foregoing semiconductor device is also proposed.

Semiconductor device and method for fabricating the same

A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

Test fixture for semiconductor package and test method of using the same

A window-type ball grid array (WBGA) semiconductor package is proposed. A substrate is formed with an opening and a tape attach area around the opening. A polyimide tape having an aperture is applied over the tape attach area, allowing the aperture to be aligned with the opening of the substrate. A chip is mounted over the polyimide tape and electrically connected to the substrate via the opening by bonding wires, wherein the polyimide tape is interposed between the chip and the substrate so as not to leave any gaps between the chip and the substrate. A first encapsulant is formed to fill the opening and encapsulate the bonding wires. A second encapsulant is fabricated to encapsulate the chip. With no gaps between the chip and the substrate, the chip is firmly supported on the substrate during a molding process for fabricating the second encapsulant, thereby preventing chip cracks from occurrence.

Window-type ball grid array semiconductor package

A fabrication method for a circuit board is proposed, wherein a core layer is formed with a plurality of conductive traces, and photo resist is applied on terminals of the conductive traces. A non-solderable material is peelably applied over a support member, and attached to the core layer to cover the conductive traces, wherein adhesion between the support member and the non-solderable material is smaller than adhesion between the non-solderable material and the core layer. Then, the support member is peeled to expose the non-solderable material; further, the non-solderable material is partly removed to expose the photo resist. Finally, the photo resist is etched away to expose the terminals of the conductive traces. The exposed terminals serve as bond pads or fingers where solder balls, bumps or wires are bonded for electrical connection purpose.

Fabrication method for circuit board

A window-type semiconductor package and a fabrication method thereof are provided. A substrate having an opening is mounted with at least a chip in a manner that, a conductive area of an active surface of the chip is exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. A non-conductive material is applied over the conductive area of the chip. An upper encapsulant is formed to encapsulate the chip, and a lower encapsulant is formed to encapsulate the bonding wires and the non-conductive material. The non-conductive material interposed between the chip and the lower encapsulant helps prevent the chip from cracking at end portions thereof due to shrinkage of the lower encapsulant, and also helps secure the bonding wires in position within the opening of the substrate without causing wire-sweeping, such that reliability and yield of the semiconductor package can be assured.

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Hsinchu, Taiwan

Jin-Chuan Bai