Taiwan Semiconductor Manufacturing Comp. Ltd.

Jin-Aun Ng

Bao-Ru Young

Harry-Hak-Lay Chuang

Maxi Chang

Ming Zhu

Po-Nien Chen

Huan-Just Lin

Pei-Ren Jeng

Chih-Tang Peng

Jen-Sheng Yang

Yi-Shien Mor

Yuan-Tien Tu

Ta-Wei Lin

Chih-Yang Yeh

Jung-Hui Kao

Hui-Wen Lin

Shih-Hao Lo

Huai-Hsien Chiu

Yi-Juei Lee

Chi-Hsin Chang

Chih-Han Lin

Kuo-Cheng Chiang

Chao-Cheng Chen

Ming-Ching Chang

Harry Chuang

Jr-Jung Lin

Chien-Liang Chen

Wei Cheng Wu

Hak-Lay Chuang

Wen-Chih Yang

Chia-Ming Liang

Chi-Wen Liu

Carlos H Diaz

Tzu-Chiang Chen

Hung-Li Chiang

Chii-Horng Li

Jean-Pierre Colinge

Ryan Chia-Jen Chen

I-Sheng Chen

Chien-Hao Chen

Tung-Ying Lee

Kuo-Tai Huang

Yu-Chao Lin

Sheng-Chen Chung

Hao-Ming Lien

Jun-Lin Yeh

Kang-Cheng Lin

Yu-Ying Hsu

Chia Ming Liang

Sin-Hua Wu

Chung-Hau Fei

Chi-Ju Lee

Chi Hsin Chang

Chun Ming Lin

Sai-Hooi Yeong

Harry Hak-Lay Chuang

Kai-Shyang You

Ssu-Yi Li

Ssu-Yu Li

Wen-Chin Yang

Chung-Hua Fei

Chien-Hau Fei

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and multiple nanostructures over the substrate. The semiconductor device structure also includes a semiconductor fin between the substrate and the nanostructures. The semiconductor device structure further includes a gate stack wrapped around the nanostructures. The gate stack includes a gate dielectric layer, and the gate dielectric layer continuously extends along a bottommost nanostructure of the nanostructures and an upper portion of the semiconductor fin.

Semiconductor device structure with hybrid fins

A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.

Semiconductor structure

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.

Silicon and silicon germanium nanowire formation

An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Integrated circuit structure

Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.

Metal gate electrode of a semiconductor device

Semiconductor structure and method for forming the same

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.

Structure and formation method of semiconductor device with hybrid fins

A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a plurality of first nanostructures, a plurality of second nanostructures, two tensile epitaxial structures, two compressive epitaxial structures, and a dielectric layer over the substrate. The method includes forming a gate dielectric layer over the first nanostructures and the second nanostructures. The method includes forming a first work function metal layer over the gate dielectric layer over the first nanostructures. The method includes forming a second work function metal layer over the gate dielectric layer over the second nanostructures. The method includes forming a compressive gate electrode layer over the first work function metal layer using an atomic layer deposition process or a chemical vapor deposition process. The method includes forming a tensile gate electrode layer over the second work function metal layer using a physical vapor deposition process.

Method for forming semiconductor device structure with gate electrode layer

A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Self-aligned insulated film for high-K metal gate device

A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Method of forming semiconductor structure

Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.

Fin critical dimension loading optimization

An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.

Self-aligned insulated film for high-k metal gate device

Growing community of inventors

Hsinchu, Taiwan

Jin-Aun Ng