Intel Corporation

Jihperng Leu

Grant M Kloster

Lee D Rockford

Markus Kuhn

Hyun-Mog Park

Jose A Maiz

Xiaorong Morrow

Patrick R Morrow

Michael D Goodner

Chris E Barns

David H Gracias

Peter K Moon

Jun He

Lawrence D Wong

Andrew W Ott

Christopher D Thomas

Chih-I Wu

Chia-Hong Jan

Mitchell C Taylor

Ying Zhou

Thomas N Marieb

Kevin P O'brien

Paul McGregor

David W Staines

Carolyn Block

Xiarong Morrow

Patrick Marrow

Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.

Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects

An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous matrix using supercritical carbon dioxide leaving voids in positions previously occupied by portions of the sacrificial dielectric layer. The resultant structure has a desirably low k value as a result of the voids and materials comprising the porous matrix and other structures. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

Formation of interconnect structures by removing sacrificial material with supercritical carbon dioxide

A method for forming a mechanically robust dielectric film comprises depositing a dielectric film on a substrate and then inducing a compressive strain in a top surface of the dielectric film to form a compressive strained surface. The compressive strain may be induced using an ion implantation process that bombards the dielectric film with ions that become implanted in the top surface of the dielectric film. The damage caused during ion implantation, as well as the implanted ions themselves, causes an expansion of the top surface which induces a biaxial compressive residual stress, thereby forming a compressive strained surface. The compressive strain reduces the amount of surface flaws present on the top surface, thereby improving the toughness of the dielectric film. In addition, the ion implantation process may modify the plasticity of the top surface and reduce the likelihood of fracture mechanisms based on dislocation pileup for crack initiation.

Mechanically robust dielectric film and stack

Metal-metal oxide etch stop/barrier for integrated circuit interconnects

The present invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.

Semiconductor device using an interconnect

A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying permeable material. As a result, at least one void is created, contributing to desirable dielectric characteristics.

Low-K dielectric structure and method

An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

Selectively converted inter-layer dielectric

A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.

Method of making semiconductor device using a novel interconnect cladding layer

In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

Mechanically robust interconnect for low-k dielectric material using post treatment

The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is disposed above and on the diffusion barrier layer. The etch stop layer has a second thickness and a second dielectric constant.

Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer

The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; forming an opening in the dielectric; and forming a conductor in the opening. The present invention further discloses a structure including a substrate; a dielectric located over the substrate, the dielectric having a k value of 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; an opening located in the dielectric; and a conductor located in the opening.

Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate&#x2014;therein

Method of forming a selectively converted inter-layer dielectric using a porogen material

A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.

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Portland, OR, United States of America

Jihperng Leu