Chartered Semiconductor Manufacturing Ltd (corporation)

Jie Yu

Yelehanka Ramachandramurthy Pradeep

Mei Sheng Zhou

Henry Gerung

Guan Ping Wu

John Leonard Sudijono

Ying Keung Leung

Vladislav Y Vassiliev

Chiew Wah Yap

Pei Ching Lee

Tjin Tjin Tjoa

Jun Qian

Kelvin Wei Loong Loh

Minghui Fan

Vijay Kumar Chhagan

A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or inorganic or organic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as a doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a silicon source to gas additive mole ratio, which is maintained depending on the used compound and deposition process conditions. Inorganic halide-containing compounds are used as gas additives. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with. good film integrity and void-free gap-fill within the steps of device structures.

Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability

A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process continues by etching the etch stop layer not protected by the spacers. The source and drain electrodes are then formed by implanting ions into the substrate not protected by the gate structure and sidewall spacers. Adjustment of the spacer width is accomplished by adjusting the total thickness of the etch stop and spacer oxide layers. Spacer width variation is controlled by changing the deposition thickness of the first spacer oxide layer.

Method of forming spacers of multiple widths

A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.

Method for forming an L-shaped spacer with a disposable organic top coating

A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provided over the liner oxide layer. The invention's nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprises the following conditions: a Cl,flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, a backside He pressure between 4 and 10 torr; and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr; at a power between 300 and 600 Watts. The etch recipe provides a spacer width to nitride layer thickness ratio of about 1:1 and does not pit the Si substrate surface.

High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness

A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900&deg; C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.

Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer

A new method of forming silicon nitride sidewall spacers has been achieved. This method is used to fabricate tapered, L-shaped spacer profiles using a two-step etching process that can be performed insitu. In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. An isolation region is provided overlying a semiconductor substrate. Conductive traces are provided overlying the insulator layer. A liner oxide layer is deposited overlying the conductive traces and the insulator layer. A silicon nitride layer is deposited overlying the liner oxide layer. The silicon nitride layer is anisotropically etched down to reduce the vertical thickness of the silicon nitride layer while not exposing the underlying liner oxide layer. The silicon nitride layer is etched through to form silicon nitride sidewall spacers adjacent to the conductive traces. This etching through results in a tapered, L-shaped sidewall profile, and the integrated circuit device is completed.

Method to form an L-shaped silicon nitride sidewall spacer

A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.

Self-aligned floating gate for memory application using shallow trench isolation

A method for fabricating a high-density high-capacity capacitor is described. A dielectric layer is provided overlying a semiconductor substrate. A sacrificial layer is deposited overlying the dielectric layer and patterned to form a pattern having a large surface area within a small area on the substrate. In one alternative, spacers are formed on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. A bottom capacitor plate layer is conformally deposited overlying the spacers. In a second alternative, a bottom capacitor plate layer is deposited overlying the patterned sacrificial layer and etched to leave spacers on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. In both alternatives, a capacitor dielectric layer is deposited overlying the bottom capacitor plate layer. A top capacitor plate layer is deposited overlying the capacitor dielectric layer and patterned to complete fabrication of a high-density high-capacity capacitor.

Method for forming high-density high-capacity capacitor

A method for forming an L-shaped spacer using a sacrificial organic top coating, then using the L-shaped spacer to simultaneously implant lightly doped source and drain extensions through the L-shaped spacer while implanting source and drain regions beyond the L-shaped spacer. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiments, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer. Impurity ions are implanted into the surface of the semiconductor structure forming lightly doped source and drain extensions where the ions are implanted through the L-shaped spacer, and forming source and drain regions beyond the L-shaped spacer where the ions are implanted without passing through the L-shaped spacer.

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Singapore, Singapore

Jie Yu