Marvell International Limited

Jie Du

Vincent M Wong

Jitendra Kumar Swarnkar

Jing Booth

A system and method of buffer management may employ a common data structure that is recognizable by both hardware and firmware. In some implementations, hardware register settings may be programmed independent of firmware updates to an internal sub-segment description table maintained in an ASIC or other buffer manager logic. Implementation of such a common data structure in external memory may substantially reduce hardware real estate and complexity of a buffer manager ASIC by minimizing the number of required registers and eliminating the need for an internal sub-segment descriptor table. In addition, by eliminating the internal sub-segment descriptor table and allowing buffer manager logic to recognize a common data structure in external memory, the number of buffer sub-segments recognized by the buffer manager may be readily expanded, and may be limited only by the size of the external memory.

Unlimited sub-segment support in a buffer manager

A controller for scan testing a memory. The controller includes a control state machine for controlling the scan process, a test sequence stored in a random access memory used by the control state machine for controlling an actual memory test, a pattern generation data unit responsive to the control state machine for generating a test pattern that is written to and read from a memory under test, a configuration register read by the control state machine for configuring the controller and a fault location register written to by the control state machine for storing locations of defects in the memory. The controller is used to auto scan a memory in real time, interleaved with other processes accessing the memory. The controller has several modes of operation including operating in a periodic burst mode to conserve power and in a background mode so as not to interfere with other processes accessing the scanned memory.

Automated scan testing of DDR SDRAM

The transfer of data from a host computer to a recordable disk in a disk drive operating on the host computer is managed. A buffer for temporarily storing data to be transferred between the host computer and the recordable disk is maintained, wherein the buffer comprises a plurality of host segments and a plurality of disk segments, and wherein each of the host segments and disk segments have a sector count value associated therewith. In a case where the transfer of data corresponds to a host segment, the host segment is selected from the plurality of host segments in the buffer. In a case where the transfer of data corresponds to a disk segment, the disk segment is selected from the plurality of disk segments in the buffer. In a case where a host segment is selected, the sector count value of the selected host segment is adjusted. In a case where a disk segment is selected, the sector count value of the selected disk segment is adjusted. Thus, the amount of hardware resources is seen to be reduced, and expansion of segmentation is seen to be improved.

Buffer management system and method

A computer system for writing data to a memory is disclosed. The memory controller in the computer system comprises a system clock, which is generated by the memory controller. A first register captures the lower data word based on the rising edge of the system clock. A second register, coupled to the first register, captures the output of the first register based on the rising edge of the system clock. A third register, captures the upper data word based on the falling edge of the system clock. A forth register, coupled to the third register, captures the output of the third register based on the falling edge of the system clock. A first multiplexer is coupled to a forth register and a second register. A delay element, coupled to the system clock and a first multiplexer, adjusts the phase of the system clock. A second multiplexer, coupled to the system clock, generates a data strobe.

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Santa Clara, CA, United States of America

Jie Du