University of Electronic Science and Technology of China

Jianwen Cao

Bo Zhang

Zekun Zhou

Zhuo Wang

Yue Shi

Yunkun Wang

He Tang

Hongming Yu

Anqi Wang

A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

Multi-level gate driver applied to SiC MOSFET

A level shifter includes a power supply rail conversion block, an RS latch and a digital detection block. The power supply rail conversion block comprises a first NLDMOS transistor, a second NLDMOS transistor, a first PLDMOS transistor, a second PLDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter. A gate of the first NLDMOS transistor is connected to an input of the first inverter, a drain of the first NLDMOS transistor is connected to a drain of the first PLDMOS transistor; a source of the first NLDMOS transistor and a source of the second NLDMOS are connected to a referenced ground of an LV power supply rail. The digital detection block comprises a second inverter, a third inverter, a first delay chain, a second delay chain, a first NAND gate and a second NAND gate.

Level shifter for high-speed gate drivers

A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased Vgenerating circuit generate the voltage Vwhich has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to &#x3bc;Tthrough the V. Finally, the reference voltage Vis obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage Vof this application can realize approximative zero temperature coefficient in the temperature range of &#x2212;40&#xb0; C.100&#xb0; C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from &#x3bc;W level to nW level and realize low power consumption.

CMOS subthreshold reference circuit with low power consumption and low temperature drift

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Chengdu, China

Jianwen Cao