Cypress Semiconductor Corporation

Applied Materials, Inc.

Advanced Ion Beam Technology, Inc.

Advanced Optical Solutions, Inc.

Jianmin Qiao

Turgut Sahin

Laxman Murugesh

Maciek Orczyk

Bo Jin

Sam G Geha

Alain Paul Blosse

Jiong Chen

James E Nulty

Sanjay M Thekdi

Mehran G Sedigh

Yitzhak Gilboa

Sanjay Thedki

Pravin Narawankar

Pravin K Narwankar

Jun Zhao

Tom K Cho

Siamak Salimian

Xin Sheng Guo

Peiching Ling

Zhimin Wan

Manuj Rathor

Alex Schreiber

Shahin Sharifzadeh

Paul Arleo

Atsushi Tabata

Jihliang Chen

Guofu Jeff Feng

A dual damascene interconnect structure, produced using etch chemistry based on CHF, includes (i) an etch stop layer of either undoped silicon oxide or doped silicon oxide, and (ii) dielectric layers both above and below the etch stop layer of the other (i.e., when the etch stop layer comprises undoped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise a doped silicon oxide; and when the etch stop layer comprises doped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise an undoped silicon oxide).

Dual damascene structure and method of making

A method and system for processing wafers is disclosed. According to one embodiment () a chuck system () may be situated opposite to an input source (). A chuck system () may apply a force (e.g., mechanical and/or electromagnetic) that deforms a substrate (). Once deformed, essentially all of a substrate () may be oriented at a predetermined angle (e.g., 90&#xb0;) with respect to an input source ().

Semiconductor processing chamber substrate holder method and structure

A method is provided for forming a self aligned contact by etching an opening through a low doped or undoped dielectric layer such as phosphosilicate glass. The dielectric layer may be formed on a semiconductor layer which may include regions of monocrystalline silicon and undoped silicon dioxide. A first portion of a dielectric layer may be etched with a first etch chemistry, and a second portion of the dielectric layer may be etched with a second etch chemistry. The first etch chemistry may be substantially different than the second etch chemistry. In this manner, the first etch chemistry may have a substantially different etch selectivity than the second etch chemistry. For example, in an embodiment, the first etch chemistry may be selective to silicon nitride, and the second etch chemistry may be selective to undoped silicon oxide. Therefore, by using multiple etch chemistries to etch a single dielectric layer, a self aligned contact having optimized properties such as sidewall angle, aspect ratio, and critical dimension may be formed while an etch stop liner layer such as a silicon nitride layer may be eliminated.

Method of forming self aligned contacts

According to one embodiment ( ), a method of forming a self-aligned contact can include forming adjacent conducting structures with sidewalls ( ). A first insulating layer may then be formed without first forming a liner ( ), such as a liner that is conventionally formed to protect underlying conducting structures and/or a substrate. A contact hole may then be etched between adjacent conducting structures ( ). Contact structures may then be formed ( ).

Semiconductor structure and method of making contacts in a semiconductor structure

A method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including C H F , in which x&gE;2, y&gE;2, and z&gE;2 is provided. Such an etch chemistry may be selective to the barrier layer. For example, the etch chemistry may have a dielectric layer:barrier layer selectivity of at least approximately 20:1, but may range from approximately 20:1 to approximately 50:1. Therefore, etching a dielectric layer with such an etch chemistry may terminate upon exposing an upper surface of the barrier layer. As such, a thickness of a barrier layer used to protect an underlying layer may be reduced to, for example, approximately 100 angstroms to approximately 150 angstroms. In addition, critical dimensions of contact openings formed with such an etch chemistry may be substantially uniform across a wafer. Furthermore, critical dimensions of contact openings formed with such an etch chemistry may be uniform from wafer to wafer.

Method for etching a dielectric layer formed upon a barrier layer

The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.

Method of making metallization and contact structures in an integrated circuit

A thin film deposition apparatus and method are disclosed in this invention. The apparatus includes a depositing thin-film particle source, a beam-defining aperture between the particle source and the deposited substrate(s), and a substrate holder to rotate the substrate(s) around its center and move the center along a lateral path so that the substrate(s) can scan across the particle beam from one substrate edge to the other edge. The method includes a step of providing a vacuum chamber for containing a thin-film particle source for generating thin-film particles to deposit a thin-film on the substrates. The method further includes a step of containing a substrate holder in the vacuum chamber for holding a plurality of substrates having a thin-film deposition surface of each substrate facing the beam of thin-film particles. The method further includes a step of providing a rotational means for rotating the substrate holder to rotate each of the substrates exposed to the thin-film particles for depositing a thin film thereon. And, the method further includes a step of providing a laterally reciprocal moving means for reciprocally moving said substrate holder for said beam traversing on said substrate holder from one side of the edge to the other side of the edge or at least passing through the central area of said substrate holder.

Apparatus and method for uniformly depositing thin films over substrates

The invention concerns a method for simultaneously forming a metallization and contact structure in an integrated circuit. The method involves the steps of etching a trench dielectric layer of a composite structure having a semiconductor substrate with an active region, a gate structure thereon, at least one dielectric spacer adjacent to the gate structure, a contact dielectric layer over the semiconductor substrate, the gate structure and the dielectric spacer, an etch stop layer over the contact dielectric layer, and a trench dielectric layer over the etch stop layer, to form a trench in the trench dielectric under etch conditions which do not substantially etch the etch stop layer; thereafter, forming an opening in the etch stop layer and the contact dielectric layer by etching under conditions which do not damage the gate structure to expose the active region; and depositing a conductive material into the opening and the trench.

Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer

A low dielectric constant insulating film on a substrate is formed by introducing a process gas comprising a silicon source, a fluorine source, and oxygen into a chamber. The process gas is formed into a plasma to deposit at least a first portion of the insulating film over the substrate. The wafer and the first portion of the insulating film are then heated to a temperature of about 100-500&deg; C. for a period of time. The film may include several separate portions, the deposition of each of which is followed by a heating step. The film has a low dielectric constant and good gas-fill and stability due to the lack of free fluorine in the film.

Sequential in-situ heating and deposition of halogen-doped silicon oxide

An electrostatic or mechanical chuck assembly includes gas inlets only in an annulus-shaped peripheral portion and not in the central region of the chuck. The gas inlets are in fluid communication with one or more gas conduits and supply of the backside of a workpiece, such as a semiconductor wafer, with inert coolant gas or gases. The gas or gases supplied only to the peripheral region of the chuck effectively cool the central region of the chuck by at least two physical mechanisms, including the thermal conduction through the workpiece and diffusion of the gas or gases in the interstitial space(s) between the somewhat irregular facing surfaces of the chuck and of the backside of the workpiece.

ELECTROSTATIC OR MECHANICAL CHUCK ASSEMBLY CONFERRING IMPROVED TEMPERATURE UNIFORMITY ONTO WORKPIECES HELD THEREBY, WORKPIECE PROCESSING TECHNOLOGY AND/OR APPARATUS CONTAINING THE SAME, AND METHOD(S) FOR HOLDING AND/OR PROCESSING A WORKPIECE WITH THE SAME

A plasma etch chemistry and etch methodology is provided to improve critical dimension control for openings formed into and/or through a semiconductor thin film. According to an embodiment, the plasma etch chemistry includes an etchant mixture comprising a first etchant of the formula C H F (where x&gE;2, y&gE;1 and z&gE;2) and a second etchant other than the first etchant to form the openings. The relationship of x, y and z may be such that y&plus;z equals an even number &lE;2x&plus;2. According to an alternative embodiment, the plasma etch chemistry further includes strained cyclic (hydro)fluorocarbon. The plasma etch chemistry may be used to form openings in the layer in a single-etch step. In a further embodiment, the plasma etch chemistry described herein may etch less than the entire thickness of the layer, and a second plasma etch chemistry substantially free of the first etchant and strained cyclic (hydro)fluorocarbons etches the remainder of the layer to form the openings. Such an etch methodology advantageously reduces the risk of etching the materials underlying the layer.

Plasma etch chemistry and method of improving etch control

According to one embodiment ( ), a method of manufacturing a semiconductor device may include forming diffusion regions in a substrate with a gate, first spacer, and second spacer as a diffusion mask ( ). A second spacer may then be removed ( ) prior to the formation of an interlayer dielectric. An interlayer dielectric may then be formed ( ) over a gate structure and first spacer. A contact hole may then be etched through the interlayer dielectric that is self-aligned with the gate ( ).

Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device

A method for conditioning a plasma etch chamber is presented. A plasma etch chamber is provided, which preferably includes a chuck for supporting a topography. A conditioning process may be performed in the etch chamber. The conditioning process preferably includes positioning a cover topography on or above the chuck. A conditioning feed gas containing (hydro)halocarbons may be introduced into the chamber. A conditioning plasma may be generated from the conditioning feed gas for a conditioning time. Immediately after generating the conditioning plasma is complete, the overall thickness of the cover topography is preferably at least as great as immediately before generating the conditioning plasma. By performing a conditioning process in such a manner, the total cost and complexity of the conditioning process may be reduced.

Method for conditioning a plasma etch chamber

A low dielectric constant insulating film on a substrate is formed by introducing a process gas comprising a silicon source, a fluorine source, and oxygen into a chamber. The process gas is formed into a plasma to deposit at least a first portion of the insulating film over the substrate. The wafer and the first portion of the insulating film are then heated to a temperature of about 100-500&deg; C. for a period of time. The film may include several separate portions, the deposition of each of which is followed by a heating step. The film has a low dielectric constant and good gap-fill and stability due to the lack of free fluorine in the film.

An insulating film with a low dielectric constant is more quickly formed on a substrate by reducing the co-etch rate as the film is deposited. The process gas is formed into a plasma from silicon-containing and fluorine-containing gases. The plasma is biased with an RF field to enhance deposition of the film. Deposition and etching occur simultaneously. The relative rate of deposition to etching is increased in the latter portion of the deposition process by decreasing the bias RF power, which decreases the surface temperature of the substrate and decreases sputtering and etching activities. Processing time is reduced compared to processes with fixed RF power levels. Film stability, retention of water by the film, and corrosion of structures on the substrate are all improved. The film has a relatively uniform and low dielectric constant and may fill trenches with aspect ratios of at least 4:1 and gaps less than 0.5 .mu.m.

Growing community of inventors

Fremont, CA, United States of America

Jianmin Qiao