Micron Technology Incorporated

Sandisk Technologies Inc.

Micron Techology, Inc.

Jianmin Huang

Xiangang Luo

Kulachet Tanpairoj

Ting Luo

Harish Reddy Singidi

Kishore Kumar Muchherla

Ashutosh Malshe

Preston Allen Thomson

Chris Avila

Steven Theodore Sprouse

Sebastien Andre Jean

Jung Sheng Hoei

Tomoko Ogura Iwasaki

Dana Lee

Gautam Ashok Dusija

Nian Niles Yang

Aparna U Limaye

Avani F Trivedi

Tracy D Evans

Sampath K Ratnam

Zhengang Chen

Niles Yang

Peter Sean Feeley

Jun Wan

Scott Anthony Stoller

Chun Sum Yeung

Chris Nga Yee Avila

Yichao Huang

Jian Feng Chen

Vamsi Pavan Rayaprolu

Mrinal Kochar

Uday Chandrasekhar

Lee M Gavens

Ankit Vinod Vashi

Idan Alrod

Deping He

Carla L Christensen

Abhijeet Manohar

Bo Lei

Giuseppe D'Eliseo

Alessandro Magnavacca

Xiaolai Zhu

Andrea Pozzato

Patroclo Fumagalli

Sergey Anatolievich Gorobets

Zhenming Zhou

Gerrit Jan Hemink

Christopher Joseph Bueb

Michael G Miller

Xinde Hu

Phong Sy Nguyen

Farookh Moogat

Tao Liu

Guang Hu

Emilio Yero

Sri Rama Namala

Alexandra Bauche

Falgun G Trivedi

Bhuvan Khurana

John Zhang

Tyson M Stichka

Neil David Hutchinson

Eran Sharon

Masaaki Higashitani

Jonathan Scott Parry

Daniel Edward Tuers

Aaron Lee

Grishma Shah

Changyuan Chen

William S Wu

Zhongguang Xu

Guirong Liang

Shai Traister

Lawrence Celso Miranda

Evgeny Mekhanik

Sheyang Ning

Steven S Cheng

Alexander Kwok-Tung Mak

Sung-Yong Chung

Neil David Hutchison

Ashish Ghai

Oleg Kragel

Alexander K Mak

Lakshmi Kalpana Vakati

Yi-Chieh Chen

Dennis S Ea

Hong Lu

Jia Ye

Swati Bakshi

Lakshmi Kalpana K Vakati

Huachen Li

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having first subset of word line groups (WGRs) that are categorized as being non-defective. The controller searches for a second PGB in the set of memory components having a second subset of WGRs that are categorized as being non-defective. The controller computes a total quantity of WGRs based on the first quantity of WGRs in the first subset of WGRs and a second quantity of WGRs in the second subset of WGRs and, in response, combines the first PGB and the second PGB to form an individual virtual block.

Generating virtual blocks using partial good blocks

Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

Source address memory managment

A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

Virtual indexing in a memory device

Methods, systems, and devices for data migration techniques are described. The memory system may receive a command associated with a write operation from a host device. The memory system may determine whether to use a data migration technique for writing data to the memory device based on receiving the command. In some cases, the memory system may select a tri-level write format instead of a quad-level write format for writing the data and write the data using the tri-level write format. The memory system may convert the data from the tri-level write format to the quad-level write format based on writing the data using the tri-level write format.

Data migration techniques

Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

Self-seeded randomizer for data randomization in flash memory

An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

Memory sub-system for monitoring mixed mode blocks

A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.

Dynamic superblock construction

A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.

Memory sub-system refresh

An example apparatus includes a media management superblock component configured to determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks; compare the quantity of bad blocks to a bad block criteria; and write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria. The use of the superblock with a particular quantity of bad block minimizes yield loss for non-use of partial superblocks.

Memory sub-system using partial superblocks

A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Reactive read based on metrics to screen defect prone memory blocks

A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.

Managing storage of multiple plane parity data in a memory sub-system

A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

Memory sub-system data migration

A system can include a memory device, and a processing device, operatively coupled with the memory device, to perform operations of writing a first portion of data to one or more complete translation units of the memory device using a first number of logical levels per memory cell and writing a second portion of the data to one or more incomplete translation units of the memory device using the first number of logical levels per memory cell. The operations can also include writing a third portion of the data to one or more complete translation units of the memory device using a second number of logical levels per memory cell that exceeds the first number of logical levels per memory cell.

Using incomplete super blocks for increased write performance

Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

UFS based idle time garbage collection management

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San Carlos, CA, United States of America

Jianmin Huang